| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 259 unsigned &Op3) { in Decode3OpInstruction() argument
269 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
538 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
539 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
543 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
551 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
552 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
556 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
564 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
565 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySelectionDAGInfo.h | 27 SDValue Op3, unsigned Align, bool isVolatile,
33 SDValue Op3, unsigned Align, bool isVolatile,
38 SDValue Op3, unsigned Align, bool IsVolatile,
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| D | WebAssemblySelectionDAGInfo.cpp | 38 SDValue Op3, unsigned Align, bool IsVolatile, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, Align, in EmitTargetCodeForMemmove()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
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| D | SelectionDAG.h | 1218 SDValue Op3);
1220 SDValue Op3, SDValue Op4);
1222 SDValue Op3, SDValue Op4, SDValue Op5);
1247 SDValue Op1, SDValue Op2, SDValue Op3);
1284 SDValue Op1, SDValue Op2, SDValue Op3);
1290 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1297 SDValue Op3);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
111 if (Op3.isGlobal()) in getAddressFromInstr()
112 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
114 AM.Disp = Op3.getImm(); in getAddressFromInstr()
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| D | X86FastISel.cpp | 181 unsigned Op2, bool Op2IsKill, unsigned Op3,
3980 unsigned Op3, bool Op3IsKill) { in fastEmitInst_rrrr() argument
3987 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
3994 .addReg(Op3, getKillRegState(Op3IsKill)); in fastEmitInst_rrrr()
4000 .addReg(Op3, getKillRegState(Op3IsKill)); in fastEmitInst_rrrr()
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| D | X86ISelDAGToDAG.cpp | 5278 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
5286 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
5294 OutOps.push_back(Op3); in SelectInlineAsmMemoryOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreSelectionDAGInfo.h | 26 SDValue Op3, unsigned Align, bool isVolatile,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/AsmParser/ |
| D | BPFAsmParser.cpp | 269 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
270 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
276 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 57 SDValue Op3, unsigned Align, bool isVolatile,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 78 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
85 switch (Op3.getImm()) { in printInst()
118 if (Op2.isImm() && Op3.isImm()) { in printInst()
122 int64_t imms = Op3.getImm(); in printInst()
152 if (Op2.getImm() > Op3.getImm()) { in printInst()
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1227 T2 Op3; member
1229 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1230 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1236 Op3.match(I->getOperand(2)); in match()
1793 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1794 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
1800 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
1802 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4509 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4510 if (Op2.isScalarReg() && Op3.isImm()) { in MatchAndEmitInstruction()
4511 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
4531 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
4532 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
4533 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4595 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4598 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4599 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
4614 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 28 bit Op3 = 0;
54 let TSFlags{5} = Op3;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1233 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1237 Register Rt = Op3.getReg(); in expandPostRAPseudo()
1241 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1257 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1266 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1276 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1280 .add(Op3); in expandPostRAPseudo()
1291 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1300 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1313 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
[all …]
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| D | HexagonSplitDouble.cpp | 908 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
909 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
910 int64_t Sh64 = Op3.getImm(); in splitAslOr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 344 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
345 (inst $Op1, $Op2, $Op3)>;
350 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
351 (inst $Op1, $Op2, $Op3, $Op4)>;
361 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, (vt3 ImmTy:$Op3))),
362 (inst $Op1, $Op2, ImmTy:$Op3)>;
367 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
368 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
1649 def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b:$idx))),
1650 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b:$idx)>;
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 134 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 224 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
231 TmpInst.addOperand(Op3); in emitRRRX()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 2288 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall3() local
2294 V.fusedMultiplyAdd(Op2->getValueAPF(), Op3->getValueAPF(), in ConstantFoldScalarCall3()
2305 if (const auto *Op3 = dyn_cast<ConstantInt>(Operands[2])) { in ConstantFoldScalarCall3() local
2318 unsigned Scale = Op3->getValue().getZExtValue(); in ConstantFoldScalarCall3()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 7674 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
7675 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
7681 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
7682 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
7688 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
7689 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
7782 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
7784 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
7989 SDValue Op3) { in getMachineNode() argument
7991 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
[all …]
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| D | SelectionDAGBuilder.cpp | 5848 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5858 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
5869 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5875 SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
5884 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5894 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
6437 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6439 Op1.getValueType(), Op1, Op2, Op3)); in visitIntrinsicCall()
6446 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6448 Op1, Op2, Op3, DAG, TLI)); in visitIntrinsicCall()
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| D | LegalizeIntegerTypes.cpp | 275 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); in PromoteIntRes_AtomicCmpSwap() local
280 N->getBasePtr(), Op2, Op3, N->getMemOperand()); in PromoteIntRes_AtomicCmpSwap()
1719 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3)); in PromoteIntOp_PREFETCH() local
1722 Op2, Op3, Op4), in PromoteIntOp_PREFETCH()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | Verifier.cpp | 4713 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); in visitIntrinsicCall() local
4714 Assert(Op3->getType()->getBitWidth() <= 32, in visitIntrinsicCall()
4720 Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
4724 Assert(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
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