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Searched refs:OpSize16 (Results 1 – 13 of 13) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrControl.td28 "ret{w}", []>, OpSize16;
34 "ret{w}\t$amt", []>, OpSize16;
40 "{l}ret{w|f}", []>, OpSize16;
46 "{l}ret{w|f}\t$amt", []>, OpSize16;
52 OpSize16;
66 "jmp\t$dst", []>, OpSize16;
83 []>, OpSize16, TB;
129 OpSize16, Sched<[WriteJump]>;
132 OpSize16, Sched<[WriteJumpLd]>;
163 OpSize16, Sched<[WriteJump]>, NOTRACK;
[all …]
DX86InstrShiftRotate.td24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
41 OpSize16;
58 "shl{w}\t$dst", []>, OpSize16;
75 OpSize16;
93 OpSize16;
110 OpSize16;
128 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16;
143 OpSize16;
158 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize16;
175 OpSize16;
[all …]
DX86InstrSystem.td74 OpSize16;
84 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
93 OpSize16;
103 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
166 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
176 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
196 OpSize16, NotMemoryFoldable;
199 OpSize16, NotMemoryFoldable;
220 OpSize16, NotMemoryFoldable;
223 OpSize16, NotMemoryFoldable;
[all …]
DX86InstrExtension.td16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
28 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
41 TB, OpSize16, Sched<[WriteALU]>;
45 TB, OpSize16, Sched<[WriteALULd]>;
67 TB, OpSize16, Sched<[WriteALU]>;
71 TB, OpSize16, Sched<[WriteALULd]>;
96 []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
99 []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
103 []>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable;
106 []>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable;
[all …]
DX86InstrInfo.td1209 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable;
1217 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable;
1252 OpSize16;
1258 OpSize16, NotMemoryFoldable;
1265 OpSize16;
1272 OpSize16;
1278 OpSize16, NotMemoryFoldable;
1284 "push{w}\t$imm", []>, OpSize16;
1286 "push{w}\t$imm", []>, OpSize16;
1298 OpSize16;
[all …]
DX86InstrArithmetic.td20 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16;
70 []>, OpSize16, Sched<[WriteIMul16]>;
96 "mul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul16>;
116 OpSize16, Sched<[WriteIMul16]>;
134 "imul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul16>;
158 Sched<[WriteIMul16Reg]>, TB, OpSize16;
178 Sched<[WriteIMul16Reg.Folded, WriteIMul16Reg.ReadAfterFold]>, TB, OpSize16;
206 Sched<[WriteIMul16Imm]>, OpSize16;
212 Sched<[WriteIMul16Imm]>, OpSize16;
245 Sched<[WriteIMul16Imm.Folded]>, OpSize16;
[all …]
DX86InstrCMovSetCC.td24 TB, OpSize16;
44 timm:$cond, EFLAGS))]>, TB, OpSize16;
DX86InstrTSX.td29 "xbegin\t$dst", []>, OpSize16;
DX86InstrCompiler.td385 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16,
404 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16,
426 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16,
449 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16,
698 OpSize16, LOCK;
723 OpSize16, LOCK;
754 OpSize16, LOCK;
801 OpSize16, LOCK;
818 OpSize16, LOCK;
860 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK;
[all …]
DX86InstrFormats.td171 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
185 class OpSize16 { OperandSize OpSize = OpSize16; }
DX86InstrSSE.td5677 Sched<[WritePOPCNT]>, OpSize16, XS;
5682 Sched<[WritePOPCNT.Folded]>, OpSize16, XS;
6591 int_x86_sse42_crc32_32_16>, OpSize16;
6593 int_x86_sse42_crc32_32_16>, OpSize16;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h700 OpSize16 = 1 << OpSizeShift, enumerator
DX86MCCodeEmitter.cpp1303 (STI.hasFeature(X86::Mode16Bit) ? X86II::OpSize32 : X86II::OpSize16)) in emitOpcodePrefix()