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Searched refs:OpSize32 (Results 1 – 13 of 13) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrControl.td24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
53 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
[all …]
DX86InstrSystem.td77 OpSize32;
87 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
96 OpSize32;
106 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
168 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
178 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
205 OpSize32, NotMemoryFoldable;
208 OpSize32, NotMemoryFoldable;
228 OpSize32, NotMemoryFoldable;
231 OpSize32, NotMemoryFoldable;
[all …]
DX86InstrShiftRotate.td27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
45 OpSize32;
60 "shl{l}\t$dst", []>, OpSize32;
79 OpSize32;
97 OpSize32;
114 OpSize32;
131 [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
147 OpSize32;
161 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32;
179 OpSize32;
[all …]
DX86InstrInfo.td1211 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1219 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1254 OpSize32, Requires<[Not64BitMode]>;
1260 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1267 OpSize32, Requires<[Not64BitMode]>;
1274 OpSize32, Requires<[Not64BitMode]>;
1280 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1289 "push{l}\t$imm", []>, OpSize32,
1292 "push{l}\t$imm", []>, OpSize32,
1300 OpSize32, Requires<[Not64BitMode]>;
[all …]
DX86InstrArithmetic.td26 OpSize32, Requires<[Not64BitMode]>;
32 OpSize32, Requires<[In64BitMode]>;
76 OpSize32, Sched<[WriteIMul32]>;
100 "mul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
120 OpSize32, Sched<[WriteIMul32]>;
138 "imul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
163 Sched<[WriteIMul32Reg]>, TB, OpSize32;
184 Sched<[WriteIMul32Reg.Folded, WriteIMul32Reg.ReadAfterFold]>, TB, OpSize32;
218 Sched<[WriteIMul32Imm]>, OpSize32;
224 Sched<[WriteIMul32Imm]>, OpSize32;
[all …]
DX86InstrCMovSetCC.td30 TB, OpSize32;
49 timm:$cond, EFLAGS))]>, TB, OpSize32;
DX86InstrTSX.td31 "xbegin\t$dst", []>, OpSize32;
DX86InstrCompiler.td389 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32,
408 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32,
431 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32,
454 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32,
668 Requires<[Not64BitMode]>, OpSize32, LOCK,
706 OpSize32, LOCK;
731 OpSize32, LOCK;
762 OpSize32, LOCK;
805 OpSize32, LOCK;
822 OpSize32, LOCK;
[all …]
DX86InstrFormats.td172 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
186 class OpSize32 { OperandSize OpSize = OpSize32; }
DX86InstrSSE.td5687 Sched<[WritePOPCNT]>, OpSize32, XS;
5693 Sched<[WritePOPCNT.Folded]>, OpSize32, XS;
6595 int_x86_sse42_crc32_32_32>, OpSize32;
6597 int_x86_sse42_crc32_32_32>, OpSize32;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h701 OpSize32 = 2 << OpSizeShift, enumerator
DX86MCCodeEmitter.cpp1303 (STI.hasFeature(X86::Mode16Bit) ? X86II::OpSize32 : X86II::OpSize16)) in emitOpcodePrefix()