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Searched refs:Opc (Results 1 – 25 of 247) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp47 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
69 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
97 Opc = Mips::CFC1; in copyPhysReg()
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DMips16InstrInfo.cpp73 unsigned Opc = 0; in copyPhysReg() local
77 Opc = Mips::MoveR3216; in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
83 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
86 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
88 assert(Opc && "Cannot copy registers"); in copyPhysReg()
90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
115 unsigned Opc = 0; in storeRegToStack() local
117 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
118 assert(Opc && "Register class not handled!"); in storeRegToStack()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp748 unsigned Opc; in SelectAddrSpaceCast() local
752 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; in SelectAddrSpaceCast()
755 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_shared_yes_6432 in SelectAddrSpaceCast()
760 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_const_yes_6432 in SelectAddrSpaceCast()
765 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_local_yes_6432 in SelectAddrSpaceCast()
770 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), in SelectAddrSpaceCast()
777 unsigned Opc; in SelectAddrSpaceCast() local
781 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64 in SelectAddrSpaceCast()
785 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_shared_yes_3264 in SelectAddrSpaceCast()
790 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_const_yes_3264 in SelectAddrSpaceCast()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h114 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
487 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
488 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
512 static inline bool isVPTOpcode(int Opc) { in isVPTOpcode() argument
513 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
514 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
515 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
516 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
517 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || in isVPTOpcode()
518 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || in isVPTOpcode()
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DARMFastISel.cpp429 unsigned Opc; in ARMMaterializeFP() local
432 Opc = ARM::FCONSTD; in ARMMaterializeFP()
435 Opc = ARM::FCONSTS; in ARMMaterializeFP()
439 TII.get(Opc), DestReg).addImm(Imm)); in ARMMaterializeFP()
454 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) in ARMMaterializeFP()
472 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
477 TII.get(Opc), ImmReg) in ARMMaterializeInt()
488 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
493 TII.get(Opc), ImmReg) in ARMMaterializeInt()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp386 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in materializeLoadStoreOperands() local
388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) in materializeLoadStoreOperands()
605 unsigned Opc = in fastMaterializeAlloca() local
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
624 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in fastMaterializeConstant() local
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
659 unsigned Opc; in fastLowerArguments() local
666 Opc = WebAssembly::ARGUMENT_i32; in fastLowerArguments()
670 Opc = WebAssembly::ARGUMENT_i64; in fastLowerArguments()
674 Opc = WebAssembly::ARGUMENT_f32; in fastLowerArguments()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCSEMIRBuilder.cpp51 bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const { in canPerformCSEForOpc()
53 if (!CSEInfo || !CSEInfo->shouldCSE(Opc)) in canPerformCSEForOpc()
83 unsigned Opc) const { in profileMBBOpcode()
87 B.addNodeIDOpcode(Opc); in profileMBBOpcode()
90 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything() argument
95 profileMBBOpcode(B, Opc); in profileEverything()
137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() argument
141 switch (Opc) { in buildInstr()
160 if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(), in buildInstr()
172 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI())) in buildInstr()
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DCSEInfo.cpp36 bool CSEConfigFull::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
37 switch (Opc) { in shouldCSEOpc()
66 bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
67 return Opc == TargetOpcode::G_CONSTANT; in shouldCSEOpc()
164 void GISelCSEInfo::countOpcodeHit(unsigned Opc) { in countOpcodeHit() argument
166 if (OpcodeHitTable.count(Opc)) in countOpcodeHit()
167 OpcodeHitTable[Opc] += 1; in countOpcodeHit()
169 OpcodeHitTable[Opc] = 1; in countOpcodeHit()
218 bool GISelCSEInfo::shouldCSE(unsigned Opc) const { in shouldCSE()
220 if (!isPreISelGenericOpcode(Opc)) in shouldCSE()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp158 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits() argument
159 switch (Opc) { in getBranchDisplacementBits()
439 unsigned Opc = 0; in canFoldIntoCSel() local
456 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
466 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
484 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
490 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
494 return Opc; in canFoldIntoCSel()
623 unsigned Opc = 0; in insertSelect() local
628 Opc = AArch64::CSELXr; in insertSelect()
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DAArch64ConditionalCompares.cpp619 unsigned Opc = 0; in convert() local
623 Opc = AArch64::SUBSWri; in convert()
627 Opc = AArch64::SUBSXri; in convert()
632 const MCInstrDesc &MCID = TII->get(Opc); in convert()
651 unsigned Opc = 0; in convert() local
657 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break; in convert()
658 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break; in convert()
659 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break; in convert()
660 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break; in convert()
661 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break; in convert()
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DAArch64ConditionOptimizer.cpp217 static int getComplementOpc(int Opc) { in getComplementOpc() argument
218 switch (Opc) { in getComplementOpc()
244 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
248 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri); in adjustCmp()
263 Opc = getComplementOpc(Opc); in adjustCmp()
266 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp)); in adjustCmp()
273 unsigned Opc; in modifyCmp() local
275 std::tie(Imm, Opc, Cmp) = Info; in modifyCmp()
280 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc)) in modifyCmp()
DAArch64InstrInfo.h83 static bool isUnscaledLdSt(unsigned Opc);
90 static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
93 static int getMemScale(unsigned Opc);
100 static unsigned getLoadStoreImmIdx(unsigned Opc);
107 static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
352 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode() argument
354 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
355 switch (Opc) { in isCondBranchOpcode()
371 static inline bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument
372 return Opc == AArch64::BR; in isIndirectBranchOpcode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
457 unsigned Opc; in PPCEmitLoad() local
482 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
485 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
489 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
491 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
495 Opc = PPC::LD; in PPCEmitLoad()
501 Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; in PPCEmitLoad()
504 Opc = FP64LoadOpc; in PPCEmitLoad()
517 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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DPPCCTRLoops.cpp148 unsigned Opc = I->getOpcode(); in verifyCTRBranch() local
149 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { in verifyCTRBranch()
210 unsigned Opc = MII->getOpcode(); in runOnMachineFunction() local
211 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || in runOnMachineFunction()
212 Opc == PPC::BDZ8 || Opc == PPC::BDZ) in runOnMachineFunction()
DPPCReduceCRLogicals.cpp391 unsigned Opc = MI.getOpcode(); in isCRLogical() local
392 return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR || in isCRLogical()
393 Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV || in isCRLogical()
394 Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET || in isCRLogical()
395 Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET; in isCRLogical()
500 unsigned Opc = UseMI.getOpcode(); in createCRLogicalOpInfo() local
501 if (Opc == PPC::ISEL || Opc == PPC::ISEL8) in createCRLogicalOpInfo()
503 if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR || in createCRLogicalOpInfo()
504 Opc == PPC::BCLRn) in createCRLogicalOpInfo()
680 unsigned Opc = CRI.MI->getOpcode(); in splitBlockOnBinaryCROp() local
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DPPCInstrInfo.cpp982 unsigned Opc; in copyPhysReg() local
984 Opc = PPC::OR; in copyPhysReg()
986 Opc = PPC::OR8; in copyPhysReg()
988 Opc = PPC::FMR; in copyPhysReg()
990 Opc = PPC::MCRF; in copyPhysReg()
992 Opc = PPC::VOR; in copyPhysReg()
1002 Opc = PPC::XXLOR; in copyPhysReg()
1005 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; in copyPhysReg()
1007 Opc = PPC::QVFMR; in copyPhysReg()
1009 Opc = PPC::QVFMRs; in copyPhysReg()
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DPPCPreEmitPeephole.cpp83 unsigned Opc = BBI->getOpcode(); in removeRedundantLIs() local
84 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS && in removeRedundantLIs()
85 Opc != PPC::LIS8) in removeRedundantLIs()
124 if (AfterBBI->getOpcode() != Opc) in removeRedundantLIs()
186 unsigned Opc = MI.getOpcode(); in runOnMachineFunction() local
187 if (Opc == PPC::UNENCODED_NOP) { in runOnMachineFunction()
192 if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) { in runOnMachineFunction()
193 const MCInstrDesc &MCID = TII->get(Opc); in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCFrameLowering.cpp138 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
140 Opc = ARC::SUB_rru6; in emitPrologue()
142 Opc = ARC::SUB_rrs12; in emitPrologue()
143 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
255 unsigned Opc = ARC::SUB_rrlimm; in emitEpilogue() local
257 Opc = ARC::SUB_rru6; in emitEpilogue()
258 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP) in emitEpilogue()
283 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
285 Opc = ARC::ADD_rru6; in emitEpilogue()
287 Opc = ARC::ADD_rrs12; in emitEpilogue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FastISel.cpp97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
131 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
333 unsigned Opc = 0; in X86FastEmitLoad() local
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
340 Opc = X86::MOV16rm; in X86FastEmitLoad()
343 Opc = X86::MOV32rm; in X86FastEmitLoad()
347 Opc = X86::MOV64rm; in X86FastEmitLoad()
351 Opc = HasAVX512 ? X86::VMOVSSZrm_alt : in X86FastEmitLoad()
355 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
359 Opc = HasAVX512 ? X86::VMOVSDZrm_alt : in X86FastEmitLoad()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DXRayInstrumentation.cpp96 unsigned Opc = 0; in replaceRetWithPatchableRet() local
101 Opc = TargetOpcode::PATCHABLE_RET; in replaceRetWithPatchableRet()
106 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in replaceRetWithPatchableRet()
108 if (Opc != 0) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
129 unsigned Opc = 0; in prependRetWithPatchableExit() local
132 Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT; in prependRetWithPatchableExit()
135 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in prependRetWithPatchableExit()
137 if (Opc != 0) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/
DWebAssemblyMCTargetDesc.h150 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { in GetDefaultP2AlignAny() argument
151 switch (Opc) { in GetDefaultP2AlignAny()
364 inline unsigned GetDefaultP2Align(unsigned Opc) { in GetDefaultP2Align() argument
365 auto Align = GetDefaultP2AlignAny(Opc); in GetDefaultP2Align()
372 inline bool isArgument(unsigned Opc) { in isArgument() argument
373 switch (Opc) { in isArgument()
402 inline bool isCopy(unsigned Opc) { in isCopy() argument
403 switch (Opc) { in isCopy()
422 inline bool isTee(unsigned Opc) { in isTee() argument
423 switch (Opc) { in isTee()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp117 unsigned getPredForm(unsigned Opc);
119 bool isScalarCmp(unsigned Opc);
143 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm() argument
146 switch (Opc) { in getPredForm()
188 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
189 if (getPredForm(Opc) != 0) in isConvertibleToPredForm()
196 switch (Opc) { in isConvertibleToPredForm()
211 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
212 switch (Opc) { in collectPredicateGPR()
257 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp141 unsigned Opc = UseMI.getOpcode(); in isInlineConstantIfFolded() local
142 switch (Opc) { in isInlineConstantIfFolded()
149 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in isInlineConstantIfFolded()
151 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 || in isInlineConstantIfFolded()
152 Opc == AMDGPU::V_FMAC_F16_e64; in isInlineConstantIfFolded()
153 bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 || in isInlineConstantIfFolded()
154 Opc == AMDGPU::V_FMAC_F32_e64; in isInlineConstantIfFolded()
156 unsigned Opc = IsFMA ? in isInlineConstantIfFolded() local
159 const MCInstrDesc &MadDesc = TII->get(Opc); in isInlineConstantIfFolded()
334 unsigned Opc = MI->getOpcode(); in tryAddToFoldList() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Utils/
DRISCVMatInt.h21 unsigned Opc; member
24 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} in Inst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DConstantFoldingMIRBuilder.h28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
31 switch (Opc) {
53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
69 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);

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