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Searched refs:OutputCount (Results 1 – 24 of 24) sorted by relevance

/third_party/node/deps/v8/src/compiler/backend/
Dregister-allocator-verifier.cc18 return instr->InputCount() + instr->OutputCount() + instr->TempCount(); in OperandCount()
91 for (size_t i = 0; i < instr->OutputCount(); ++i, ++count) { in RegisterAllocatorVerifier()
150 for (size_t i = 0; i < instr->OutputCount(); ++i, ++count) { in VerifyAssignment()
585 for (size_t i = 0; i < instr->OutputCount(); ++i, ++count) { in VerifyGapMoves()
Dmove-optimizer.cc178 for (size_t i = 0; i < instruction->OutputCount(); ++i) { in RemoveClobberedDestinations()
229 for (size_t i = 0; i < from->OutputCount(); ++i) { in MigrateMoves()
389 if (last_instr->OutputCount() != 0) return; in OptimizeMerge()
Dinstruction.h850 size_t OutputCount() const { return OutputCountField::decode(bit_field_); } in OutputCount() function
852 DCHECK_LT(i, OutputCount()); in OutputAt()
856 DCHECK_LT(i, OutputCount()); in OutputAt()
860 bool HasOutput() const { return OutputCount() > 0; } in HasOutput()
867 return &operands_[OutputCount() + i]; in InputAt()
871 return &operands_[OutputCount() + i]; in InputAt()
877 return &operands_[OutputCount() + InputCount() + i]; in TempAt()
881 return &operands_[OutputCount() + InputCount() + i]; in TempAt()
Dinstruction-scheduler.h199 return (instr->arch_opcode() == kArchNop) && (instr->OutputCount() == 1) && in IsFixedRegisterParameter()
Dinstruction.cc513 if (instr.OutputCount() == 1) { in operator <<()
515 } else if (instr.OutputCount() > 1) { in operator <<()
517 for (size_t i = 1; i < instr.OutputCount(); i++) { in operator <<()
787 for (size_t i = 0; i < instruction->OutputCount(); ++i) { in ValidateSSA()
Dinstruction-scheduler.cc196 for (size_t i = 0; i < instr->OutputCount(); ++i) { in AddInstruction()
Dmid-tier-register-allocator.cc2884 for (size_t i = 0; i < instr->OutputCount(); i++) { in DefineOutputs()
3036 for (size_t i = 0; i < instr->OutputCount(); i++) { in AllocateRegisters()
3170 for (size_t i = 0; i < instr->OutputCount(); i++) { in ReserveFixedRegisters()
Dregister-allocator.cc1669 for (size_t i = 0; i < last_instruction->OutputCount(); i++) { in MeetRegisterConstraintsForLastInstructionInBlock()
1719 for (size_t i = 0; i < first->OutputCount(); i++) { in MeetConstraintsAfter()
1820 for (size_t i = 0; i < second->OutputCount(); i++) { in MeetConstraintsBefore()
2141 for (size_t i = 0; i < instr->OutputCount(); i++) { in ProcessInstructions()
Dcode-generator.cc1067 return_count = static_cast<int>(iter->instruction()->OutputCount()); in BuildTranslationForFrameStateDescriptor()
/third_party/skia/third_party/externals/angle2/src/libANGLE/
DOverlayWidgets.cpp202 static std::ostream &OutputCount(std::ostream &out, const overlay::Count *count);
365 OutputCount(text, validationMessageCount); in AppendVulkanValidationMessageCount()
490 std::ostream &AppendWidgetDataHelper::OutputCount(std::ostream &out, const overlay::Count *count) in OutputCount() function in gl::overlay_impl::AppendWidgetDataHelper
/third_party/node/deps/v8/src/compiler/backend/s390/
Dcode-generator-s390.cc35 size_t OutputCount() { return instr_->OutputCount(); } in OutputCount() function in v8::internal::compiler::S390OperandConverter
142 return instr->OutputCount() > 0 && instr->OutputAt(index)->IsRegister(); in HasRegisterOutput()
2103 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2108 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2118 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2124 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2162 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2168 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2178 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2183 if (i.OutputCount() > 1) { in AssembleArchInstruction()
[all …]
/third_party/node/deps/v8/src/compiler/backend/riscv64/
Dcode-generator-riscv64.cc1426 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1431 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1436 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1441 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1446 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1451 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1456 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1462 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1490 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1496 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
[all …]
Dinstruction-scheduler-riscv64.cc1397 return TruncLSLatency(instr->OutputCount() > 1); in GetInstructionLatency()
1399 return TruncLDLatency(instr->OutputCount() > 1); in GetInstructionLatency()
/third_party/node/deps/v8/src/compiler/backend/mips/
Dcode-generator-mips.cc351 instr->OutputCount() >= 1 ? i.OutputRegister(0) : i.TempRegister(1); \
353 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(2); \
380 instr->OutputCount() >= 1 ? i.OutputRegister(0) : i.TempRegister(1); \
382 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(2); \
1083 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1096 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1109 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1865 if (instr->OutputCount() > 0) { in AssembleArchInstruction()
1866 Register second_output = instr->OutputCount() == 2 in AssembleArchInstruction()
1926 instr->OutputCount() >= 1 ? i.OutputRegister(0) : i.TempRegister(1); in AssembleArchInstruction()
[all …]
/third_party/node/deps/v8/src/compiler/backend/arm/
Dcode-generator-arm.cc575 DCHECK_GE(instr->OutputCount() + instr->TempCount(), 2); in VerifyOutputOfAtomicPairInstr()
576 if (instr->OutputCount() == 2) { in VerifyOutputOfAtomicPairInstr()
580 if (instr->OutputCount() == 1) { in VerifyOutputOfAtomicPairInstr()
586 DCHECK_EQ(instr->OutputCount(), 0); in VerifyOutputOfAtomicPairInstr()
1257 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1269 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1281 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
3428 if (instr->OutputCount() == 2) { in AssembleArchInstruction()
3436 DCHECK_EQ(instr->OutputCount(), 1); in AssembleArchInstruction()
3627 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
[all …]
/third_party/node/deps/v8/src/compiler/backend/x64/
Dcode-generator-x64.cc1171 Register reg = i.OutputRegister(instr->OutputCount() - 1); in ShouldClearOutputRegisterBeforeInstruction()
1192 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchInstruction()
2016 if (instr->OutputCount() == 1) { in AssembleArchInstruction()
2024 DCHECK_EQ(2, instr->OutputCount()); in AssembleArchInstruction()
2076 if (instr->OutputCount() == 1) { in AssembleArchInstruction()
2084 DCHECK_EQ(2, instr->OutputCount()); in AssembleArchInstruction()
2136 if (instr->OutputCount() > 1) __ Move(i.OutputRegister(1), 0); in AssembleArchInstruction()
2142 if (instr->OutputCount() > 1) __ Move(i.OutputRegister(1), 1); in AssembleArchInstruction()
2148 if (instr->OutputCount() > 1) __ Move(i.OutputRegister(1), 0); in AssembleArchInstruction()
2154 if (instr->OutputCount() > 1) __ Move(i.OutputRegister(1), 1); in AssembleArchInstruction()
[all …]
/third_party/node/deps/v8/src/compiler/backend/arm64/
Dcode-generator-arm64.cc63 size_t OutputCount() { return instr_->OutputCount(); } in OutputCount() function in v8::internal::compiler::Arm64OperandConverter
1747 if (i.OutputCount() > 1) { in AssembleArchInstruction()
1761 DCHECK_IMPLIES(set_overflow_to_min_i64, i.OutputCount() == 1); in AssembleArchInstruction()
1768 } else if (i.OutputCount() > 1) { in AssembleArchInstruction()
1778 if (i.OutputCount() > 1) { in AssembleArchInstruction()
1787 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2944 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
2945 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/third_party/node/deps/v8/src/compiler/backend/loong64/
Dcode-generator-loong64.cc1368 bool load_status = instr->OutputCount() > 1; in AssembleArchInstruction()
1389 bool load_status = instr->OutputCount() > 1; in AssembleArchInstruction()
1432 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1439 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
2008 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
2009 Register result = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/third_party/node/deps/v8/src/compiler/backend/mips64/
Dinstruction-scheduler-mips64.cc1593 return TruncLSLatency(instr->OutputCount() > 1); in GetInstructionLatency()
1595 return TruncLDLatency(instr->OutputCount() > 1); in GetInstructionLatency()
Dcode-generator-mips64.cc1508 bool load_status = instr->OutputCount() > 1; in AssembleArchInstruction()
1528 bool load_status = instr->OutputCount() > 1; in AssembleArchInstruction()
1529 DCHECK_IMPLIES(set_overflow_to_min_i64, instr->OutputCount() == 1); in AssembleArchInstruction()
1570 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1577 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
3949 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
3950 Register result = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/third_party/node/deps/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc36 size_t OutputCount() { return instr_->OutputCount(); } in OutputCount() function in v8::internal::compiler::PPCOperandConverter
1271 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1283 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1297 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1848 (opcode == kPPC_DoubleToInt64 && i.OutputCount() > 1); in AssembleArchInstruction()
1887 bool check_conversion = (i.OutputCount() > 1); in AssembleArchInstruction()
3921 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
3922 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/third_party/node/deps/v8/src/compiler/backend/ia32/
Dcode-generator-ia32.cc599 if (instr->OutputCount() == 2) { in VerifyOutputOfAtomicPairInstr()
603 if (instr->OutputCount() == 1) { in VerifyOutputOfAtomicPairInstr()
609 DCHECK_EQ(instr->OutputCount(), 0); in VerifyOutputOfAtomicPairInstr()
3821 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
3822 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/third_party/node/deps/v8/src/compiler/
Dgraph-visualizer.cc1259 for (size_t i = 0; i < instr->OutputCount(); i++) { in operator <<()
Dpipeline.cc3548 instr->InputCount(), instr->OutputCount()); in VerifyGeneratedCodeIsIdempotent()