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Searched refs:PhysReg (Results 1 – 25 of 94) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegAllocFast.cpp87 MCPhysReg PhysReg = 0; ///< Currently held here. member
140 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
143 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
144 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
149 bool isRegUsedInInstr(MCPhysReg PhysReg) const { in isRegUsedInInstr()
150 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
198 void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg,
200 unsigned calcSpillCost(MCPhysReg PhysReg) const;
201 void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
218 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
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DLiveRegMatrix.cpp81 LiveInterval &VRegInterval, unsigned PhysReg, in foreachUnit() argument
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
106 << printReg(PhysReg, TRI) << ':'); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
124 << printReg(PhysReg, TRI) << ':'); in unassign()
127 foreachUnit(TRI, VirtReg, PhysReg, in unassign()
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DReachingDefAnalysis.cpp43 for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) { in enterBasicBlock()
172 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { in getReachingDef() argument
180 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { in getReachingDef()
191 MachineInstr* ReachingDefAnalysis::getReachingMIDef(MachineInstr *MI, int PhysReg) { in getReachingMIDef() argument
192 return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)); in getReachingMIDef()
196 int PhysReg) { in hasSameReachingDef() argument
202 return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg); in hasSameReachingDef()
222 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) { in getClearance() argument
224 return InstIds[MI] - getReachingDef(MI, PhysReg); in getClearance()
227 void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, int PhysReg, in getReachingLocalUses() argument
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DRegAllocGreedy.cpp323 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) { in addEviction() argument
325 Evictees[Evictee].second = PhysReg; in addEviction()
357 unsigned PhysReg; member
370 PhysReg = Reg; in reset()
469 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
477 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
503 unsigned PhysReg, unsigned &CostPerUseLimit,
531 unsigned PhysReg; member
533 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg) in HintInfo()
534 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
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DRegisterClassInfo.cpp111 unsigned PhysReg = RawOrder[i]; in compute() local
113 if (Reserved.test(PhysReg)) in compute()
115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
118 if (CalleeSavedAliases[PhysReg] && in compute()
119 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) in compute()
121 CSRAlias.push_back(PhysReg); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
134 unsigned PhysReg = CSRAlias[i]; in compute() local
135 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
138 RCI.Order[N++] = PhysReg; in compute()
DVirtRegMap.cpp187 void addLiveInsForSubRanges(const LiveInterval &LI, Register PhysReg) const;
267 Register PhysReg) const { in addLiveInsForSubRanges()
306 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
322 Register PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() local
323 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); in addMBBLiveIns()
326 addLiveInsForSubRanges(LI, PhysReg); in addMBBLiveIns()
336 MBB->addLiveIn(PhysReg); in addMBBLiveIns()
518 Register PhysReg = VRM->getPhys(VirtReg); in rewrite() local
519 assert(PhysReg != VirtRegMap::NO_PHYS_REG && in rewrite()
521 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); in rewrite()
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DInterferenceCache.h47 unsigned PhysReg = 0; variable
105 PhysReg = 0; in clear()
111 unsigned getPhysReg() const { return PhysReg; } in getPhysReg()
157 Entry *get(unsigned PhysReg);
212 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg() argument
216 if (PhysReg) in setPhysReg()
217 setEntry(Cache.get(PhysReg)); in setPhysReg()
DInterferenceCache.cpp67 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { in get() argument
68 unsigned E = PhysRegEntries[PhysReg]; in get()
69 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { in get()
85 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
86 PhysRegEntries[PhysReg] = E; in get()
100 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) in revalidate()
111 PhysReg = physReg; in reset()
117 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in reset()
126 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { in valid()
198 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { in update()
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DRegAllocBasic.cpp117 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
204 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
211 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in spillInterferences()
221 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) in spillInterferences()
263 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
265 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
268 return PhysReg; in selectOrSplit()
272 PhysRegSpillCands.push_back(PhysReg); in selectOrSplit()
/third_party/mesa3d/src/amd/compiler/tests/
Dtest_insert_nops.cpp30 bld.mubuf(aco_opcode::buffer_load_dword, Definition(PhysReg(256), v1), Operand(PhysReg(0), s4), in create_mubuf()
31 Operand(PhysReg(256), v1), Operand::zero(), offset, true); in create_mubuf()
38 mimg->definitions[0] = Definition(PhysReg(256), v1); in create_mimg()
39 mimg->operands[0] = Operand(PhysReg(0), s8); in create_mimg()
40 mimg->operands[1] = Operand(PhysReg(0), s4); in create_mimg()
43 mimg->operands[3 + i] = Operand(PhysReg(256 + (nsa ? i * 2 : i)), v1); in create_mimg()
126 bld.writelane(Definition(PhysReg(511), v1), Operand::zero(), Operand::zero(),
127 Operand(PhysReg(511), v1));
135 bld.writelane(Definition(PhysReg(511), v1), Operand::zero(), Operand::zero(),
136 Operand(PhysReg(511), v1));
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Dtest_hard_clause.cpp32 desc_op.setFixed(PhysReg(0)); in create_mubuf()
33 bld.mubuf(aco_opcode::buffer_load_dword, Definition(PhysReg(256), v1), desc_op, in create_mubuf()
34 Operand(PhysReg(256), v1), Operand::zero(), 0, false) in create_mubuf()
41 bld.mubuf(aco_opcode::buffer_store_dword, Operand(PhysReg(0), s4), Operand(PhysReg(256), v1), in create_mubuf_store()
42 Operand(PhysReg(256), v1), Operand::zero(), 0, false); in create_mubuf_store()
48 desc_op.setFixed(PhysReg(0)); in create_mtbuf()
49 bld.mtbuf(aco_opcode::tbuffer_load_format_x, Definition(PhysReg(256), v1), desc_op, in create_mtbuf()
50 Operand(PhysReg(256), v1), Operand::zero(), V_008F0C_BUF_DATA_FORMAT_32, in create_mtbuf()
58 bld.flat(aco_opcode::flat_load_dword, Definition(PhysReg(256), v1), in create_flat()
59 Operand(PhysReg(256), v2), Operand(s2)); in create_flat()
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Dtest_assembler.cpp37 bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0});
50 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
72 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
102 bld.sopp(aco_opcode::s_cbranch_scc0, Definition(PhysReg(0), s2), 2);
138 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 0);
166 bld.sopp(aco_opcode::s_cbranch_execnz, Definition(PhysReg(0), s2), 0);
185 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
189 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
208 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
219 bld.sop1(aco_opcode::p_constaddr_getpc, Definition(PhysReg(0), s2), Operand::zero());
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Dtest_to_hw_instr.cpp29 PhysReg v0_lo{256};
30 PhysReg v0_hi{256};
31 PhysReg v0_b1{256};
32 PhysReg v0_b3{256};
33 PhysReg v1_lo{257};
34 PhysReg v1_hi{257};
35 PhysReg v1_b1{257};
36 PhysReg v1_b3{257};
37 PhysReg v2_lo{258};
38 PhysReg v3_lo{259};
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Dtest_regalloc.cpp95 op.setFixed(PhysReg(2));
109 op.setFixed(PhysReg(1));
126 op.setFixed(PhysReg(2));
143 op.setFixed(PhysReg(2));
194 PhysReg reg_v0{256};
195 PhysReg reg_v1{257};
217 PhysReg reg_v1{257};
221 …p = bld.pseudo(aco_opcode::p_unit_test, bld.def(s1, scc), Definition(s0_tmp.id(), PhysReg{0}, s1));
248 PhysReg reg_v2{258};
249 PhysReg reg_v4{260};
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Dtest_optimizer_postRA.cpp30 PhysReg reg_v0(256);
31 PhysReg reg_s0(0);
32 PhysReg reg_s2(2);
33 PhysReg reg_s4(4);
136 PhysReg reg_s0{0};
137 PhysReg reg_s1{1};
138 PhysReg reg_s2{2};
139 PhysReg reg_s3{3};
140 PhysReg reg_s4{4};
141 PhysReg reg_s6{6};
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DReachingDefAnalysis.h96 int getReachingDef(MachineInstr *MI, int PhysReg);
100 MachineInstr *getReachingMIDef(MachineInstr *MI, int PhysReg);
107 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg);
111 bool isReachingDefLiveOut(MachineInstr *MI, int PhysReg);
116 int PhysReg);
120 bool isRegUsedAfter(MachineInstr *MI, int PhysReg);
123 MachineInstr *getInstWithUseBefore(MachineInstr *MI, int PhysReg);
126 void getAllInstWithUseBefore(MachineInstr *MI, int PhysReg,
131 int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
135 void getReachingLocalUses(MachineInstr *MI, int PhysReg,
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DLiveRegMatrix.h107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
114 bool checkInterference(SlotIndex Start, SlotIndex End, unsigned PhysReg);
119 void assign(LiveInterval &VirtReg, unsigned PhysReg);
127 bool isPhysRegUsed(unsigned PhysReg) const;
139 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
144 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
108 if (!MRI->isPhysRegUsed(PhysReg) && in processDef()
109 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef()
110 Matrix->assign(LI, PhysReg); in processDef()
111 assert(PhysReg != 0); in processDef()
135 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
138 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
142 MO.setReg(PhysReg); in rewriteRegs()
153 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
154 assert(PhysReg != 0); in rewriteRegs()
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/third_party/mesa3d/src/amd/compiler/
Daco_ir.h433 struct PhysReg { struct
434 constexpr PhysReg() = default;
435 explicit constexpr PhysReg(unsigned r) : reg_b(r << 2) {} in PhysReg() function
439 constexpr bool operator==(PhysReg other) const { return reg_b == other.reg_b; } argument
440 constexpr bool operator!=(PhysReg other) const { return reg_b != other.reg_b; }
441 constexpr bool operator<(PhysReg other) const { return reg_b < other.reg_b; }
442 constexpr PhysReg advance(int bytes) const in advance() argument
444 PhysReg res = *this; in advance()
453 static constexpr PhysReg m0{124}; argument
454 static constexpr PhysReg flat_scr_lo{102}; /* GFX8-GFX9, encoded differently on GFX6-7 */
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Daco_lower_to_hw_instr.cpp199 emit_int64_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, in emit_int64_dpp_op()
200 PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask, in emit_int64_dpp_op()
204 Definition dst[] = {Definition(dst_reg, v1), Definition(PhysReg{dst_reg + 1}, v1)}; in emit_int64_dpp_op()
205 Definition vtmp_def[] = {Definition(vtmp_reg, v1), Definition(PhysReg{vtmp_reg + 1}, v1)}; in emit_int64_dpp_op()
206 Operand src0[] = {Operand(src0_reg, v1), Operand(PhysReg{src0_reg + 1}, v1)}; in emit_int64_dpp_op()
207 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; in emit_int64_dpp_op()
209 Operand vtmp_op[] = {Operand(vtmp_reg, v1), Operand(PhysReg{vtmp_reg + 1}, v1)}; in emit_int64_dpp_op()
299 emit_int64_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, in emit_int64_op()
303 Definition dst[] = {Definition(dst_reg, v1), Definition(PhysReg{dst_reg + 1}, v1)}; in emit_int64_op()
305 Operand src0[] = {Operand(src0_reg, src0_rc), Operand(PhysReg{src0_reg + 1}, src0_rc)}; in emit_int64_op()
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Daco_register_allocation.cpp46 void add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg reg);
49 PhysReg reg;
60 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {} in assignment()
111 PhysReg reg;
113 PhysReg operator*() const { return reg; } in operator *()
136 PhysReg lo_;
140 PhysReg lo() const { return lo_; } in lo()
143 PhysReg hi() const { return PhysReg{lo() + size}; } in hi()
147 lo_ = PhysReg{lo_.reg() + stride}; in operator +=()
154 static PhysRegInterval from_until(PhysReg first, PhysReg end) { return {first, end - first}; } in from_until()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp108 virtual void markPhysRegUsed(unsigned PhysReg) { in markPhysRegUsed() argument
109 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
110 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
127 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed() argument
128 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
141 Register PhysReg = VA.getLocReg(); in assignValueToReg() local
142 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { in assignValueToReg()
150 .addUse(PhysReg + (STI.isLittle() ? 0 : 1)) in assignValueToReg()
151 .addUse(PhysReg + (STI.isLittle() ? 1 : 0)) in assignValueToReg()
154 markPhysRegUsed(PhysReg); in assignValueToReg()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp124 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
126 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
136 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
146 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
257 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
259 markPhysRegUsed(PhysReg); in assignValueToReg()
270 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
274 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg); in assignValueToReg()
279 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
285 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp44 Register PhysReg = VRM->getPhys(MO.getReg()); in getRC32() local
45 if (SystemZ::GR32BitRegClass.contains(PhysReg)) in getRC32()
47 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) && in getRC32()
115 Register PhysReg = in getRegAllocationHints() local
117 if (PhysReg) { in getRegAllocationHints()
119 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
121 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
123 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)) in getRegAllocationHints()
124 TwoAddrHints.insert(PhysReg); in getRegAllocationHints()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp115 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
118 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
124 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
125 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
337 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
340 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
348 markPhysRegUsed(PhysReg); in assignValueToReg()
350 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
359 MIRBuilder.buildCopy(PhysRegToVReg, PhysReg); in assignValueToReg()
400 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
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