| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 80 class PostRAScheduler : public MachineFunctionPass { class
86 PostRAScheduler() : MachineFunctionPass(ID) {} in PostRAScheduler() function in __anonb57d78d30111::PostRAScheduler
112 char PostRAScheduler::ID = 0;
201 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
203 INITIALIZE_PASS(PostRAScheduler, DEBUG_TYPE,
266 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler()
282 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { in runOnMachineFunction()
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| D | TargetSubtargetInfo.cpp | 54 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiSchedule.td | 45 let PostRAScheduler = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCSchedule.h | 300 bool PostRAScheduler; // default value is false member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleM4.td | 18 let PostRAScheduler = 1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86Schedule.td | 705 // and disables PostRAScheduler.
711 let PostRAScheduler = 0;
717 // Define a model with the PostRAScheduler enabled.
719 let PostRAScheduler = 1;
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| D | X86ScheduleSLM.td | 21 let PostRAScheduler = 1;
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| D | X86ScheduleAtom.td | 28 let PostRAScheduler = 1;
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| D | X86ScheduleBtVer2.td | 23 let PostRAScheduler = 1;
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| D | X86.td | 1011 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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| D | X86ScheduleBdVer2.td | 29 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
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| D | X86ScheduleZnver2.td | 22 let PostRAScheduler = 1;
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| D | X86ScheduleZnver1.td | 22 let PostRAScheduler = 1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SISchedule.td | 65 let PostRAScheduler = 1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenSubtargetInfo.inc | 7808 false, // PostRAScheduler
7823 false, // PostRAScheduler
7838 false, // PostRAScheduler
7853 false, // PostRAScheduler
7868 false, // PostRAScheduler
7883 false, // PostRAScheduler
7898 false, // PostRAScheduler
7913 false, // PostRAScheduler
7928 false, // PostRAScheduler
7943 false, // PostRAScheduler
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX.td | 25 let PostRAScheduler = 1; // Use PostRA scheduler.
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| D | AArch64SchedThunderX2T99.td | 25 let PostRAScheduler = 1; // Using PostRA sched.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 90 bit PostRAScheduler = 0; // Enable Post RegAlloc Scheduler pass.
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 20843 false, // PostRAScheduler
20858 false, // PostRAScheduler
20886 true, // PostRAScheduler
20969 true, // PostRAScheduler
21032 false, // PostRAScheduler
21110 true, // PostRAScheduler
21173 false, // PostRAScheduler
21217 false, // PostRAScheduler
21280 false, // PostRAScheduler
21319 true, // PostRAScheduler
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 3635 false, // PostRAScheduler
3679 true, // PostRAScheduler
3720 false, // PostRAScheduler
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleGeneric.td | 28 let PostRAScheduler = 1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZEC12.td | 24 let PostRAScheduler = 1;
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| D | SystemZScheduleZ196.td | 24 let PostRAScheduler = 1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSubtargetInfo.inc | 13129 false, // PostRAScheduler
13166 false, // PostRAScheduler
13200 false, // PostRAScheduler
13236 false, // PostRAScheduler
13318 false, // PostRAScheduler
13428 false, // PostRAScheduler
13532 false, // PostRAScheduler
13581 false, // PostRAScheduler
13622 false, // PostRAScheduler
13656 true, // PostRAScheduler
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 18000 false, // PostRAScheduler
18015 false, // PostRAScheduler
18045 false, // PostRAScheduler
18063 false, // PostRAScheduler
18096 false, // PostRAScheduler
18124 true, // PostRAScheduler
18158 false, // PostRAScheduler
18190 false, // PostRAScheduler
|