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/third_party/libunwind/src/arm/
DGstash_frame.c43 rs->reg.where[R7], rs->reg.val[R7], DWARF_GET_LOC(d->loc[R7]), in tdep_stash_frame()
55 && (rs->reg.val[DWARF_CFA_REG_COLUMN] == R7 in tdep_stash_frame()
59 && (rs->reg.where[R7] == DWARF_WHERE_UNDEF in tdep_stash_frame()
60 || rs->reg.where[R7] == DWARF_WHERE_SAME in tdep_stash_frame()
61 || (rs->reg.where[R7] == DWARF_WHERE_CFAREL in tdep_stash_frame()
62 && labs(rs->reg.val[R7]) < (1 << 29) in tdep_stash_frame()
63 && rs->reg.val[R7]+1 != 0)) in tdep_stash_frame()
79 if (rs->reg.where[R7] == DWARF_WHERE_CFAREL) in tdep_stash_frame()
80 f->r7_cfa_offset = rs->reg.val[R7]; in tdep_stash_frame()
Dunwind_i.h35 #define R7 7 macro
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
Dcomc597.mme.h155 MME_INSN(0, MERGE, R7, ZERO, R1, (1<<10)|(5<<5)|0, ALU1, NONE,
159 MME_INSN(1, ADD, ZERO, R7, IMMED, (1<<12)|0x0600/4, ALU0, ALU1,
202 OR, R7, R1, R2, 0, NONE, NONE),
205 MME_INSN(0, AND, R7, R7, IMMED, 1, NONE, NONE,
207 MME_INSN(0, BEQ, ZERO, R7, ZERO, (2<<14)|0x0002, NONE, NONE,
215 MME_INSN(0, OR, R7, R3, R4, 0, NONE, NONE,
217 MME_INSN(0, AND, R7, R7, IMMED, 1, NONE, NONE,
219 MME_INSN(0, BEQ, ZERO, R7, ZERO, (2<<14)|0x0002, NONE, NONE,
246 OR, R7, R1, R2, 0, NONE, NONE),
249 MME_INSN(0, AND, R7, R7, IMMED, 1, NONE, NONE,
[all …]
/third_party/libdrm/data/
Damdgpu.ids70 6600, 81, AMD Radeon R7 M370
72 6604, 0, AMD Radeon R7 M265 Series
73 6604, 81, AMD Radeon R7 M350
74 6605, 0, AMD Radeon R7 M260 Series
75 6605, 81, AMD Radeon R7 M340
80 6610, 81, AMD Radeon R7 350
84 6617, C7, AMD Radeon R7 240 Series
92 6658, 0, AMD Radeon R7 200 Series
94 665D, 0, AMD Radeon R7 200 Series
95 665F, 81, AMD Radeon R7 300 Series
[all …]
/third_party/ffmpeg/libavcodec/arm/
Dsimple_idct_arm.S81 … mov r7, r1, asr #16 @ R7=R1>>16=ROWr16[1] (evaluate it now, as it could be useful later)
83 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
108 …mul r7, r11, r7 @ R7=W7*ROWr16[1]=b3 (ROWr16[1] must be the second arg, to have the possi…
116 …mlane r7, r10, r2, r7 @ R7-=W5*ROWr16[3]=b3 (ROWr16[3] must be the second arg, to have the poss…
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
144 mlane r7, r9, r3, r7 @ R7+=W3*ROWr16[5]=b3
146 mlane r1, r8, r3, r1 @ R7-=W1*ROWr16[5]=b1
153 mlane r7, r8, r4, r7 @ R7-=W1*ROWr16[7]=b3
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp42 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
DMSP430RegisterInfo.td60 def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>;
81 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
DXCoreRegisterInfo.cpp214 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/third_party/mesa3d/src/panfrost/bifrost/
DREADME.md10 R4 - R7: input (color #1)
19 R4 - R7: preloaded (message #1)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
266 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
271 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
279 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
281 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
293 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
298 // Also save R7-R4 first to match the stack frame fixed spill areas.
299 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
304 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
317 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
DThumb1FrameLowering.cpp222 case ARM::R7: in emitPrologue()
287 case ARM::R7: in emitPrologue()
683 PopFriendly.set(ARM::R7); in emitPopSpecialFixUp()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
985 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
DPPCCallingConv.td81 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
92 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
196 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
211 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/third_party/ffmpeg/libswscale/x86/
Dyuv_2_rgb.asm194 paddsw m5, m1 ; R1 R3 R5 R7 ...
202 packuswb m0, m3 ; R0 R2 R4 R6 ... R1 R3 R5 R7 ...
209 punpcklbw m6, m_red ; B0 R1 B2 R3 B4 R5 B6 R7 B8 R9 ...
214 punpckhwd m5, m6 ; R4 G4 B4 R5 R6 G6 B6 R7
221 pand m7, [mask_0110] ; -- -- R6 G6 B6 R7 -- --
247 movd [imageq + 18], m5 ; R6 G6 B6 R7
282 punpckhbw m1, m3 ; R0 R1 R2 R3 ... R7
Dinput.asm156 pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
169 movd m6, [srcq+20] ; (byte) { R6, B7, G7, R7 }
171 punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
176 punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
182 pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
270 pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
275 movd m3, [srcq+20] ; (byte) { R6, B7, G7, R7 }
277 punpckldq m5, m3 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
280 punpcklbw m5, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
284 pmaddwd m3, m5, coeffU2 ; (dword) { R4*BU, G5*GU + R5*BU, R6*BU, G7*GU + R7*BU }
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiCallingConv.td24 CCAssignToReg<[R6, R7, R18, R19]>>>>,
36 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td51 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
102 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
121 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
127 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td36 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
DARCCallingConv.td32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFFrameLowering.cpp36 SavedRegs.reset(BPF::R7); in determineCalleeSaves()
DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h59 case Lanai::R7: in getLanaiRegisterNumbering()
/third_party/ltp/testcases/kernel/syscalls/ptrace/
Dptrace04.c34 R(R0) R(R1) R(R2) R(R3) R(R4) R(R5) R(R6) R(R7)
/third_party/ffmpeg/libavcodec/x86/
Dvp3dsp.asm281 psubsw m7, m0 ; r7 = R7 = G. - C.
315 psubsw m7, m0 ; r7 = R7 = G. - C.
316 paddsw m7, OC_8 ; adjust R7 (and R0) for shift
371 punpckhdq m6, m0 ; r6 = h3 g3 f3 e3 = R7
491 psubsw m7, m0 ; xmm7 = G. - C. = R7
492 ADD(m7) ; Adjust R7 and R0 before shifting

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