Searched refs:RADEON_SURF_MAX_LEVELS (Results 1 – 5 of 5) sorted by relevance
51 #define RADEON_SURF_MAX_LEVELS 15 macro131 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];132 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];137 struct legacy_surf_dcc_level dcc_level[RADEON_SURF_MAX_LEVELS];144 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];145 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];242 uint32_t offset[RADEON_SURF_MAX_LEVELS];244 uint16_t pitch[RADEON_SURF_MAX_LEVELS];250 uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS];252 uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS];[all …]
209 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; in one_dcc_address_test()432 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; in one_htile_address_test()
1712 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {0}; in gfx9_compute_miptree()1805 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; in gfx9_compute_miptree()1898 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; in gfx9_compute_miptree()2087 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; in gfx9_compute_miptree()
508 struct cpu_texture src_cpu[RADEON_SURF_MAX_LEVELS], dst_cpu[RADEON_SURF_MAX_LEVELS]; in si_test_image_copy_region()
401 float depth_clear_value[RADEON_SURF_MAX_LEVELS];402 uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];