| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anoncb15cb830111::ARMInstructionSelector
162 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
190 const RegisterBankInfo &RBI) { in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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| D | ARMSubtarget.cpp | 116 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo()); in ARMSubtarget() local
122 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI)); in ARMSubtarget()
124 RegBankInfo.reset(RBI); in ARMSubtarget()
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| D | ARM.h | 55 const ARMRegisterBankInfo &RBI);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstructionSelector.cpp | 35 const RISCVRegisterBankInfo &RBI);
46 const RISCVRegisterBankInfo &RBI; member in __anonb8d3f4110111::RISCVInstructionSelector
70 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
72 TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
100 RISCVRegisterBankInfo &RBI) { in createRISCVInstructionSelector() argument
101 return new RISCVInstructionSelector(TM, Subtarget, RBI); in createRISCVInstructionSelector()
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| D | RISCVSubtarget.cpp | 59 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); in RISCVSubtarget() local
60 RegBankInfo.reset(RBI); in RISCVSubtarget()
62 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); in RISCVSubtarget()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 53 const AArch64RegisterBankInfo &RBI);
294 const AArch64RegisterBankInfo &RBI; member in __anon3fb655d50111::AArch64InstructionSelector
317 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
319 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
333 const RegisterBankInfo &RBI, in getRegClassForTypeOnBank() argument
431 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
457 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
586 const RegisterBankInfo &RBI) { in isValidCopy() argument
589 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in isValidCopy()
590 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in isValidCopy()
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| D | AArch64Subtarget.cpp | 182 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo()); in AArch64Subtarget() local
188 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI)); in AArch64Subtarget()
190 RegBankInfo.reset(RBI); in AArch64Subtarget()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
57 const MipsRegisterBankInfo &RBI; member in __anon97854f750111::MipsInstructionSelector
76 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
78 TRI(*STI.getRegisterInfo()), RBI(RBI), in MipsInstructionSelector()
91 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
96 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
106 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
146 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
159 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
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| D | MipsSubtarget.cpp | 214 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); in MipsSubtarget() local
215 RegBankInfo.reset(RBI); in MipsSubtarget()
217 *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI)); in MipsSubtarget()
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| D | MipsLegalizerInfo.cpp | 362 const RegisterBankInfo &RBI = *ST.getRegBankInfo(); in legalizeIntrinsic() local
377 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); in legalizeIntrinsic()
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| D | MipsRegisterBankInfo.cpp | 343 const RegisterBankInfo &RBI = in setTypesAccordingToPhysicalRegister() local
346 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI); in setTypesAccordingToPhysicalRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 62 const X86RegisterBankInfo &RBI);
135 const X86RegisterBankInfo &RBI; member in __anon47af25cf0111::X86InstructionSelector
154 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
156 TRI(*STI.getRegisterInfo()), RBI(RBI), in X86InstructionSelector()
199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
238 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
239 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
274 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) && in selectCopy()
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| D | X86Subtarget.cpp | 353 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo()); in X86Subtarget() local
354 RegBankInfo.reset(RBI); in X86Subtarget()
355 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI)); in X86Subtarget()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 50 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
53 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
141 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
153 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectCOPY()
168 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
200 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
256 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
258 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
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| D | AMDGPUInstructionSelector.h | 52 const AMDGPURegisterBankInfo &RBI,
195 const AMDGPURegisterBankInfo &RBI; variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 47 const RegisterBankInfo &RBI, unsigned Reg,
61 const RegisterBankInfo &RBI,
79 const RegisterBankInfo &RBI,
95 const RegisterBankInfo &RBI);
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| D | InstructionSelector.h | 466 const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
498 const RegisterBankInfo &RBI) const;
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| D | InstructionSelectorImpl.h | 55 const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, in executeMatchTable() argument
577 &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum), in executeMatchTable()
579 RBI.getRegBank(MO.getReg(), MRI, TRI)) { in executeMatchTable()
984 *TRI.getRegClass(RCEnum), TII, TRI, RBI); in executeMatchTable()
996 RBI); in executeMatchTable()
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| D | RegBankSelect.h | 486 const RegisterBankInfo *RBI = nullptr; variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 32 const RegisterBankInfo &RBI, unsigned Reg, in constrainRegToClass() argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
43 const RegisterBankInfo &RBI, MachineInstr &InsertPt, in constrainOperandRegClass() argument
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
73 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, in constrainOperandRegClass() argument
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
114 const RegisterBankInfo &RBI) { in constrainSelectedInstRegOperands() argument
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
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| D | RegBankSelect.cpp | 83 RBI = MF.getSubtarget().getRegBankInfo(); in init()
84 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
121 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
260 return RBI->getBreakDownCost(ValMapping, CurRegBank); in getRepairCost()
279 unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank, in getRepairCost()
280 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); in getRepairCost()
618 RBI->applyMapping(OpdMapper); in applyMapping()
630 BestMapping = &RBI->getInstrMapping(MI); in assignInstr()
637 RBI->getInstrPossibleMappings(MI); in assignInstr()
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| D | InstructionSelector.cpp | 39 const RegisterBankInfo &RBI) const { in constrainOperandRegToRegClass()
44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, in constrainOperandRegToRegClass()
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| D | RegisterBankInfo.cpp | 606 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo(); in verify() local
607 (void)RBI; in verify()
625 assert(MOMapping.verify(RBI->getSizeInBits( in verify()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | MergedLoadStoreMotion.cpp | 307 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
308 RBI != RBE;) { in mergeStores()
310 Instruction *I = &*RBI; in mergeStores()
311 ++RBI; in mergeStores()
339 RBI = Pred0->rbegin(); in mergeStores()
341 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 310 const RegisterBankInfo &RBI) const { in constrainAllUses() argument
311 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in constrainAllUses()
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