Home
last modified time | relevance | path

Searched refs:RT (Results 1 – 25 of 104) sorted by relevance

12345

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td17 bits<5> RT;
23 let Inst{6-10} = RT;
58 bits<5> RT;
64 let Inst{6-10} = RT;
104 bits<5> RT;
108 let Inst{6-10} = RT;
118 bits<5> RT;
123 let Inst{6-10} = RT;
140 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
141 "brinc $RT, $RA, $RB", IIC_IntSimple, []>;
[all …]
DPPCInstr64Bit.td373 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
374 "mfspr $RT, $SPR", IIC_SprMFSPR>;
375 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
376 "mtspr $SPR, $RT", IIC_SprMTSPR>;
790 def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
791 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
793 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
794 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
795 def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
796 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
[all …]
DPPCInstrFormats.td393 bits<5> RT;
398 let Inst{6-10} = RT;
723 // [PO RT /// RB XO RC]
771 bits<5> RT;
774 let Inst{6-10} = RT;
785 bits<5> RT;
788 let Inst{6-10} = RT;
927 // [PO RT RA RB XO /]
1126 bits<5> RT;
1131 let Inst{6-10} = RT;
[all …]
DPPCInstrInfo.td2666 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2667 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2668 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2669 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2671 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2672 "mftb $RT, $SPR", IIC_SprMFTB>;
2674 def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
2675 "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2677 def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
2678 "mtpmr $SPR, $RT", IIC_SprMTPMR>;
[all …]
/third_party/optimized-routines/math/test/
Dulp.h16 static int RT(ulpscale_mpfr) (mpfr_t x, int t) in RT() function
21 mpfr_exp_t e = mpfr_get_exp (x) - RT(prec); in RT()
22 if (e < RT(emin)) in RT()
23 e = RT(emin) - 1; in RT()
24 if (e > RT(emax) - RT(prec)) in RT()
25 e = RT(emax) - RT(prec); in RT()
29 return RT(emin) - 1; in RT()
31 return RT(emax) - RT(prec); in RT()
40 static double RT(ulperr) (RT(float) got, const struct RT(ret) * p, int r) in RT() function
42 RT(float) want = p->y; in RT()
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen7.5/
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
12 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
14 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
16 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
18 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
20 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen8/
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
12 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
14 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
16 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
18 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
20 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen7/
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
12 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
14 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
16 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
18 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
20 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen6/
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
12 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
14 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
16 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
18 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
20 render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
[all …]
/third_party/typescript/tests/baselines/reference/
DmutuallyRecursiveInference.types11 class L<RT extends { a: 'a' | 'b', b: any }> extends T<RT[RT['a']]> {
12 >L : L<RT>
15 >T : T<RT[RT["a"]]>
19 >this.a : RT[RT["a"]]
21 >a : RT[RT["a"]]
DmutuallyRecursiveInference.symbols13 class L<RT extends { a: 'a' | 'b', b: any }> extends T<RT[RT['a']]> {
15 >RT : Symbol(RT, Decl(mutuallyRecursiveInference.ts, 4, 8))
19 >RT : Symbol(RT, Decl(mutuallyRecursiveInference.ts, 4, 8))
20 >RT : Symbol(RT, Decl(mutuallyRecursiveInference.ts, 4, 8))
DmutuallyRecursiveInference.js6 class L<RT extends { a: 'a' | 'b', b: any }> extends T<RT[RT['a']]> {
/third_party/mesa3d/src/intel/tools/tests/gen9/
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
16 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
40 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
42 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
44 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
46 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
48 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
50 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen5/
Dsend.asm4 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
8 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
46 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 8 rlen 0 { align1 EOT };
48 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
60 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 7 rlen 0 { align1 EOT };
62 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
72 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 9 rlen 0 { align1 EOT };
74 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
88 write MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 };
90 write MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen4/
Dsend.asm6 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
52 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
62 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
64 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
84 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
94 write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 };
96 write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 };
98 write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 };
100 … write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT };
108 … write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen4.5/
Dsend.asm4 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
48 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
52 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
62 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
76 write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 };
78 write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 };
80 write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 };
82 … write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT };
98 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
114 … write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT };
[all …]
/third_party/typescript/tests/cases/compiler/
DmutuallyRecursiveInference.ts5 class L<RT extends { a: 'a' | 'b', b: any }> extends T<RT[RT['a']]> {
/third_party/ffmpeg/libavcodec/
Dffv1_template.c37 const int RT = last[1]; in RENAME() local
45 p->quant_table[2][(T - RT) & 0xFF] + in RENAME()
51 p->quant_table[2][(T - RT) & 0xFF]; in RENAME()
/third_party/pcre2/pcre2/src/sljit/
DsljitNativeARM_64.c56 #define RT(rt) ((sljit_ins)reg_map[rt]) macro
913 return push_inst(compiler, STRB | type | RT(reg) in emit_op_mem()
917 return push_inst(compiler, STRBI | type | RT(reg) | RN(tmp_reg)); in emit_op_mem()
927 return push_inst(compiler, STRBI | type | RT(reg) | RN(tmp_reg) | ((sljit_ins)argw << 10)); in emit_op_mem()
933 … return push_inst(compiler, STRBI | type | RT(reg) | RN(arg) | ((sljit_ins)argw << (10 - shift))); in emit_op_mem()
939 return push_inst(compiler, STRBI | type | RT(reg) | RN(tmp_reg) | ((sljit_ins)argw << 10)); in emit_op_mem()
944 return push_inst(compiler, STRBI | type | RT(reg) | RN(tmp_reg) | ((sljit_ins)argw << 10)); in emit_op_mem()
949 return push_inst(compiler, STURBI | type | RT(reg) | RN(arg) | (((sljit_ins)argw & 0x1ff) << 12)); in emit_op_mem()
954 …return push_inst(compiler, STURBI | type | RT(reg) | RN(tmp_reg) | (((sljit_ins)argw & 0x1ff) << 1… in emit_op_mem()
958 …return push_inst(compiler, STURBI | type | RT(reg) | RN(tmp_reg) | (((sljit_ins)argw & 0x1ff) << 1… in emit_op_mem()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/TableGen/
DRecord.h106 static bool classof(const RecTy *RT) { in classof() argument
107 return RT->getRecTyKind() == BitRecTyKind; in classof()
124 static bool classof(const RecTy *RT) { in classof() argument
125 return RT->getRecTyKind() == BitsRecTyKind; in classof()
146 static bool classof(const RecTy *RT) { in classof() argument
147 return RT->getRecTyKind() == CodeRecTyKind; in classof()
164 static bool classof(const RecTy *RT) { in classof() argument
165 return RT->getRecTyKind() == IntRecTyKind; in classof()
182 static bool classof(const RecTy *RT) { in classof() argument
183 return RT->getRecTyKind() == StringRecTyKind; in classof()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp691 RegisterRef RT(ST); in split() local
692 if (RT == RegisterRef(SF)) { in split()
700 MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub); in split()
957 RegisterRef RT(MS); in predicate() local
959 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
1031 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else)) in predicate()
1058 if (RT != RD) { in predicate()
1059 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt); in predicate()
1060 UpdRegs.insert(RT.Reg); in predicate()
/third_party/parse5/packages/parse5/lib/common/
Dhtml.ts136 RT = 'rt', enumerator
308 RT, enumerator
458 [TAG_NAMES.RT, TAG_ID.RT],
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DIVDescriptors.h93 Instruction *UAI, Type *RT, bool Signed, in RecurrenceDescriptor() argument
96 MinMaxKind(MK), UnsafeAlgebraInst(UAI), RecurrenceType(RT), in RecurrenceDescriptor()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/IPO/
DThinLTOBitcodeWriter.cpp259 auto *RT = dyn_cast<IntegerType>(F->getReturnType()); in splitAndWriteThinLTOBitcode() local
260 if (!RT || RT->getBitWidth() > 64 || F->arg_empty() || in splitAndWriteThinLTOBitcode()
/third_party/vk-gl-cts/external/vulkan-docs/src/appendices/
DVK_HUAWEI_invocation_mask.txt31 RT mask is updated before each traceRay.

12345