| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | Register.h | 20 unsigned Reg; variable
23 Register(unsigned Val = 0): Reg(Val) {} in Reg() function
24 Register(MCRegister Val): Reg(Val) {} in Register()
45 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
46 return MCRegister::isStackSlot(Reg); in isStackSlot()
50 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
51 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
52 return int(Reg - (1u << 30)); in stackSlot2Index()
63 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
64 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
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| D | MachineRegisterInfo.h | 60 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
125 return MO->Contents.Reg.Next; in getNextOperandForReg()
235 void disableCalleeSavedRegister(unsigned Reg);
256 void verifyUseList(unsigned Reg) const;
286 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands() argument
287 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
302 reg_instructions(unsigned Reg) const { in reg_instructions() argument
303 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
317 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles() argument
318 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); in reg_bundles()
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| D | LiveIntervals.h | 114 LiveInterval &getInterval(Register Reg) { in getInterval() argument
115 if (hasInterval(Reg)) in getInterval()
116 return *VirtRegIntervals[Reg.id()]; in getInterval()
118 return createAndComputeVirtRegInterval(Reg); in getInterval()
121 const LiveInterval &getInterval(Register Reg) const { in getInterval() argument
122 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
125 bool hasInterval(Register Reg) const { in hasInterval() argument
126 return VirtRegIntervals.inBounds(Reg.id()) && in hasInterval()
127 VirtRegIntervals[Reg.id()]; in hasInterval()
131 LiveInterval &createEmptyInterval(Register Reg) { in createEmptyInterval() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
60 VRegInfo[Reg].first = RC; in setRegClass()
63 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, in constrainRegClass() argument
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
85 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, in constrainRegAttrs() argument
95 const LLT RegTy = getType(Reg); in constrainRegAttrs()
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| D | AggressiveAntiDepBreaker.cpp | 75 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
76 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
88 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
89 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
90 Regs.push_back(Reg); in GetGroupRegs()
109 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
115 GroupNodeIndices[Reg] = idx; in LeaveGroup()
119 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
122 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
165 unsigned Reg = *AI; in StartBlock() local
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| D | CriticalAntiDepBreaker.cpp | 75 unsigned Reg = *AI; in StartBlock() local
76 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
77 KillIndices[Reg] = BBSize; in StartBlock()
78 DefIndices[Reg] = ~0u; in StartBlock()
89 unsigned Reg = *I; in StartBlock() local
90 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
93 unsigned Reg = *AI; in StartBlock() local
94 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
95 KillIndices[Reg] = BBSize; in StartBlock()
96 DefIndices[Reg] = ~0u; in StartBlock()
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| D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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| D | RegisterScavenging.cpp | 53 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) { in setRegUsed() argument
54 LiveUnits.addRegMasked(Reg, LaneMask); in setRegUsed()
77 SI.Reg = 0; in init()
100 void RegScavenger::addRegUnits(BitVector &BV, Register Reg) { in addRegUnits() argument
101 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
105 void RegScavenger::removeRegUnits(BitVector &BV, Register Reg) { in removeRegUnits() argument
106 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in removeRegUnits()
137 Register Reg = MO.getReg(); in determineKillsAndDefs() local
138 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg)) in determineKillsAndDefs()
146 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
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| D | LivePhysRegs.cpp | 85 Register Reg = O->getReg(); in stepForward() local
86 if (!Register::isPhysicalRegister(Reg)) in stepForward()
91 Clobbers.push_back(std::make_pair(Reg, &*O)); in stepForward()
96 removeReg(Reg); in stepForward()
103 for (auto Reg : Clobbers) { in stepForward() local
106 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
108 if (Reg.second->isRegMask() && in stepForward()
109 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward()
111 addReg(Reg.first); in stepForward()
140 MCPhysReg Reg) const { in available()
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| D | MachineInstrBundle.cpp | 158 Register Reg = MO.getReg(); in finalizeBundle() local
159 if (!Reg) in finalizeBundle()
162 if (LocalDefSet.count(Reg)) { in finalizeBundle()
166 KilledDefSet.insert(Reg); in finalizeBundle()
168 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
169 ExternUses.push_back(Reg); in finalizeBundle()
171 UndefUseSet.insert(Reg); in finalizeBundle()
175 KilledUseSet.insert(Reg); in finalizeBundle()
181 Register Reg = MO.getReg(); in finalizeBundle() local
182 if (!Reg) in finalizeBundle()
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| D | RegAllocFast.cpp | 221 Register traceCopyChain(Register Reg) const;
625 Register RegAllocFast::traceCopyChain(Register Reg) const { in traceCopyChain()
629 if (Reg.isPhysical()) in traceCopyChain()
630 return Reg; in traceCopyChain()
631 assert(Reg.isVirtual()); in traceCopyChain()
633 MachineInstr *VRegDef = MRI->getUniqueVRegDef(Reg); in traceCopyChain()
636 Reg = VRegDef->getOperand(1).getReg(); in traceCopyChain()
649 Register Reg = MI.getOperand(1).getReg(); in traceCopies() local
650 Reg = traceCopyChain(Reg); in traceCopies()
651 if (Reg.isValid()) in traceCopies()
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| D | TargetRegisterInfo.cpp | 58 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg) in markSuperRegs()
60 for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI) in markSuperRegs()
68 for (unsigned Reg : RegisterSet.set_bits()) { in checkAllSuperRegsMarked() local
69 if (Checked[Reg]) in checkAllSuperRegsMarked()
71 for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { in checkAllSuperRegsMarked()
72 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { in checkAllSuperRegsMarked()
74 << " of reserved register " << printReg(Reg, this) in checkAllSuperRegsMarked()
89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() argument
91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
92 if (!Reg) in printReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 78 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
79 unsigned Reg; member in __anonb9759e2c0111::GCNRegBankReassign::OperandMask
88 : MI(mi), Reg(reg), FreeBanks(freebanks), Weight(weight) {} in Candidate()
95 dbgs() << P->printReg(Reg) << " to banks "; in dump()
102 unsigned Reg; member in __anonb9759e2c0111::GCNRegBankReassign::Candidate
165 unsigned getPhysRegBank(unsigned Reg) const;
171 unsigned getRegBankMask(unsigned Reg, unsigned SubReg, int Bank);
177 unsigned Reg = AMDGPU::NoRegister, int Bank = -1);
181 bool isReassignable(unsigned Reg) const;
198 unsigned getFreeBanks(unsigned Reg, unsigned SubReg, unsigned Mask,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVectorPrint.cpp | 73 static bool isVecReg(unsigned Reg) { in isVecReg() argument
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) in isVecReg()
75 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg()
76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
95 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
99 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
107 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
111 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
112 if (isVecReg(Reg)) in getInstrVecReg()
117 Reg = MI.getOperand(2).getReg(); in getInstrVecReg()
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| D | RDFRegisters.cpp | 49 if (UnitInfos[U].Reg != 0) in PhysicalRegisterInfo()
57 UnitInfos[U].Reg = F; in PhysicalRegisterInfo()
62 UI.Reg = F; in PhysicalRegisterInfo()
101 std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const { in getAliasSet()
104 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); in getAliasSet()
105 if (isRegMaskId(Reg)) { in getAliasSet()
107 const uint32_t *MB = getRegMaskBits(Reg); in getAliasSet()
115 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
121 for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI) in getAliasSet()
125 if (aliasRM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
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| D | HexagonGenPredicate.cpp | 55 RegisterSubReg(const Register &Reg) : R(Reg), S(0) {} in RegisterSubReg()
57 bool operator== (const RegisterSubReg &Reg) const { in operator ==()
58 return R == Reg.R && S == Reg.S; in operator ==()
61 bool operator< (const RegisterSubReg &Reg) const { in operator <()
62 return R < Reg.R || (R == Reg.R && S < Reg.S); in operator <()
69 PrintRegister(RegisterSubReg R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {} in PrintRegister()
72 RegisterSubReg Reg; member
79 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
116 void processPredicateGPR(const RegisterSubReg &Reg);
121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegister.h | 23 unsigned Reg; variable
26 MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function
46 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
47 return int(Reg) >= (1 << 30); in isStackSlot()
52 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
53 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
54 return int(Reg) > 0; in isPhysicalRegister()
60 return isPhysicalRegister(Reg); in isPhysical()
64 return Reg;
68 return Reg; in id()
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| D | MCRegisterInfo.h | 67 bool contains(MCRegister Reg) const { in contains() argument
68 unsigned RegNo = unsigned(Reg); in contains()
245 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { in mc_difflist_iterator() argument
246 Iter.init(Reg, DiffList); in mc_difflist_iterator()
283 mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) in mc_subreg_iterator() argument
284 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
295 mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) in mc_superreg_iterator() argument
296 : mc_difflist_iterator(Reg, in mc_superreg_iterator()
297 MCRI->DiffLists + MCRI->get(Reg).SuperRegs) {} in mc_superreg_iterator()
302 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const { in subregs() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64TargetStreamer.h | 42 virtual void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveReg() argument
43 virtual void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegX() argument
44 virtual void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegP() argument
45 virtual void EmitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegPX() argument
46 virtual void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFReg() argument
47 virtual void EmitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegX() argument
48 virtual void EmitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegP() argument
49 virtual void EmitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegPX() argument
87 void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override;
88 void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) override;
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| D | AArch64InstPrinter.cpp | 745 unsigned Reg = MI->getOperand(OpNum++).getReg(); in printInst() local
746 if (Reg != AArch64::XZR) in printInst()
747 O << ", " << getRegisterName(Reg); in printInst()
879 unsigned Reg = Op.getReg(); in printOperand() local
880 O << getRegisterName(Reg); in printOperand()
907 unsigned Reg = Op.getReg(); in printPostIncOperand() local
908 if (Reg == AArch64::XZR) in printPostIncOperand()
911 O << getRegisterName(Reg); in printPostIncOperand()
921 unsigned Reg = Op.getReg(); in printVRegOperand() local
922 O << getRegisterName(Reg, AArch64::vreg); in printVRegOperand()
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| D | AArch64WinCOFFStreamer.cpp | 65 int Reg, in EmitARM64WinUnwindCode() argument
72 auto Inst = WinEH::Instruction(UnwindCode, Label, Reg, Offset); in EmitARM64WinUnwindCode()
96 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveReg(unsigned Reg, in EmitARM64WinCFISaveReg() argument
100 EmitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in EmitARM64WinCFISaveReg()
103 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveRegX(unsigned Reg, in EmitARM64WinCFISaveRegX() argument
105 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in EmitARM64WinCFISaveRegX()
108 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveRegP(unsigned Reg, in EmitARM64WinCFISaveRegP() argument
110 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in EmitARM64WinCFISaveRegP()
113 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveRegPX(unsigned Reg, in EmitARM64WinCFISaveRegPX() argument
115 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in EmitARM64WinCFISaveRegPX()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 Register Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
90 if (Register::isPhysicalRegister(Reg)) in getAccDefMI()
94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
100 if (Register::isVirtualRegister(Reg)) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
106 if (Register::isVirtualRegister(Reg)) { in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 122 unsigned Reg; member
135 RegOp Reg; member
171 Op->Reg.Kind = Kind; in createReg()
172 Op->Reg.Num = Num; in createReg()
196 Op->Mem.Length.Reg = LengthReg; in createMem()
223 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
227 return Reg.Num; in getReg()
328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); in addBDRAddrOperands()
408 bool parseRegister(Register &Reg);
410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 57 unsigned Reg; member
67 Address() { Base.Reg = 0; } in Address()
75 void setReg(unsigned Reg) { in setReg() argument
77 assert(Base.Reg == 0 && "Overwriting non-zero register"); in setReg()
78 Base.Reg = Reg; in setReg()
82 return Base.Reg; in getReg()
103 return Base.Reg != 0; in isSet()
157 unsigned maskI1Value(unsigned Reg, const Value *V);
159 unsigned zeroExtendToI32(unsigned Reg, const Value *V,
161 unsigned signExtendToI32(unsigned Reg, const Value *V,
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| D | WebAssemblyRegStackify.cpp | 269 static MachineInstr *getVRegDef(unsigned Reg, const MachineInstr *Insert, in getVRegDef() argument
273 if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) in getVRegDef()
277 if (const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore( in getVRegDef()
287 static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, in hasOneUse() argument
290 if (MRI.hasOneUse(Reg)) in hasOneUse()
294 const LiveInterval &LI = LIS.getInterval(Reg); in hasOneUse()
298 for (auto &I : MRI.use_nodbg_operands(Reg)) { in hasOneUse()
337 Register Reg = MO.getReg(); in isSafeToMove() local
340 if (MO.isDead() && Insert->definesRegister(Reg) && in isSafeToMove()
341 !Insert->readsRegister(Reg)) in isSafeToMove()
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