| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
73 assert(Idx == RegBank.getID() && in verify()
75 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); in verify()
76 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() local
127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
129 return &RegBank; in getRegBankFromConstraints()
268 const RegisterBank *RegBank) { in hashPartialMapping() argument
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
276 PartMapping.RegBank); in hash_value()
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| D | RegBankSelect.cpp | 122 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
263 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
604 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank); in applyMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member
66 const RegisterBank &RegBank) in PartialMapping()
67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
463 const RegisterBank &RegBank) const;
471 const RegisterBank &RegBank) const;
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| D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
93 RegBank.print(OS);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
192 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
195 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
196 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
199 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
358 unsigned RegBank, in selectLoadStoreOpCode() argument
362 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
376 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1089 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| D | ARMRegisterBankInfo.cpp | 52 PM.RegBank->getID() == RegBankID; in checkPartMapping()
475 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 522 Info.D.RegBank = nullptr; in parseRegisterInfo()
529 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
530 if (!RegBank) in parseRegisterInfo()
536 Info.D.RegBank = RegBank; in parseRegisterInfo()
605 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| D | MIParser.cpp | 298 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
300 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
1305 const RegisterBank *RegBank = nullptr; in parseRegisterClassOrBank() local
1307 RegBank = PFS.Target.getRegBank(Name); in parseRegisterClassOrBank()
1308 if (!RegBank) in parseRegisterClassOrBank()
1318 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; in parseRegisterClassOrBank()
1319 if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank) in parseRegisterClassOrBank()
1321 RegInfo.D.RegBank = RegBank; in parseRegisterClassOrBank()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 205 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1130 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingWideLoad()
1482 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1535 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1623 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1648 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1722 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1744 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1780 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingImpl()
1881 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
[all …]
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| D | AMDGPUGenRegisterBankInfo.def | 45 // StartIdx, Length, RegBank
193 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterBank.inc | 94 // Assert that RegBank indices match their ID's
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
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| D | X86InstructionSelector.cpp | 199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() local
200 return getRegClass(Ty, RegBank); in getRegClass()
1368 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues() local
1372 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1378 MRI.setRegBank(Tmp, RegBank); in selectMergeValues()
1437 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP() local
1441 unsigned Opc = getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Align); in materializeFP()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterBank.inc | 105 // Assert that RegBank indices match their ID's
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/MIRParser/ |
| D | MIParser.h | 41 const RegisterBank *RegBank; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
125 Map.RegBank == &RB;
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| D | AArch64RegisterBankInfo.cpp | 665 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank, in getInstrMapping()
666 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank, in getInstrMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterBank.inc | 130 // Assert that RegBank indices match their ID's
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterBank.inc | 148 // Assert that RegBank indices match their ID's
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 64 const RegisterBank &RegBank) { in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
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| D | MachineVerifier.cpp | 1727 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); in visitMachineOperand() local
1730 if (!RegBank && isFunctionRegBankSelected) { in visitMachineOperand()
1738 if (RegBank && Ty.isValid() && in visitMachineOperand()
1739 RegBank->getSize() < Ty.getSizeInBits()) { in visitMachineOperand()
1742 errs() << "Register bank " << RegBank->getName() << " too small(" in visitMachineOperand()
1743 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits() in visitMachineOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 673 void setRegBank(unsigned Reg, const RegisterBank &RegBank);
|