| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_ir.h | 308 struct RegClass { struct
338 RegClass() = default;
339 constexpr RegClass(RC rc_) : rc(rc_) {} in RegClass() argument
340 constexpr RegClass(RegType type, unsigned size) in RegClass() function
354 constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); } in as_linear() argument
355 constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); } in as_subdword() argument
357 static constexpr RegClass get(RegType type, unsigned bytes) in get() argument
360 return RegClass(type, DIV_ROUND_UP(bytes, 4u)); in get()
362 return bytes % 4u ? RegClass(type, bytes).as_subdword() : RegClass(type, bytes / 4u); in get()
366 constexpr RegClass resize(unsigned bytes) const in resize() argument
[all …]
|
| D | aco_instruction_selection_setup.cpp | 240 RegClass
244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
246 return RegClass::get(type, components * bitsize / 8u); in get_reg_class()
466 RegClass* regclasses = ctx->program->temp_rc.data() + ctx->first_temp_id; in init_context()
585 RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components, in init_context()
593 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
745 RegClass rc = get_reg_class(ctx, type, intrinsic->dest.ssa.num_components, in init_context()
758 RegClass rc = in init_context()
772 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
792 RegClass rc = get_reg_class(ctx, type, num_components, phi->dest.ssa.bit_size); in init_context()
|
| D | aco_reindex_ssa.cpp | 33 std::vector<RegClass> temp_rc = {s1};
44 RegClass rc = def.regClass(); in reindex_defs()
|
| D | aco_register_allocation.cpp | 41 unsigned idx, RegClass rc);
43 RegClass rc);
45 get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr, RegClass rc);
50 RegClass rc;
60 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {} in assignment()
176 get_stride(RegClass rc) in get_stride()
206 RegClass rc;
208 DefInfo(ra_ctx& ctx, aco_ptr<Instruction>& instr, RegClass rc_, int operand) : rc(rc_) in DefInfo()
222 rc = RegClass::get(rc.type(), info.second); in DefInfo()
287 void block(PhysReg start, RegClass rc) in block()
[all …]
|
| D | aco_reduce_assign.cpp | 60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
|
| D | aco_instruction_selection.h | 52 std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1)); in shader_io_state()
|
| D | aco_lower_to_hw_instr.cpp | 304 RegClass src0_rc = src0_reg.reg() >= 256 ? v1 : s1; in emit_int64_op()
391 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
431 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
1004 RegClass op_cls = src.op.regClass().resize(bytes); in split_copy()
1247 Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
1249 Definition(lo_reg, RegClass::get(RegType::vgpr, lo_half.bytes() + op.bytes())); in do_copy()
1620 RegClass rc = RegClass(it->second.def.regClass().type(), it->second.def.size() - 2); in handle_operands()
1622 rc = RegClass(it->second.op.regClass().type(), it->second.op.size() - 2); in handle_operands()
1733 RegClass::get(RegType::vgpr, other->second.bytes))); in handle_operands()
[all …]
|
| D | aco_instruction_selection.cpp | 151 RegClass rc = RegClass(mask.regClass().type(), 1); in emit_mbcnt()
347 emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc) in emit_extract_vector()
388 RegClass rc; in emit_split_vector()
396 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword(); in emit_split_vector()
398 rc = RegClass(vec_src.type(), vec_src.size() / num_components); in emit_split_vector()
422 Temp tmp_dst = bld.tmp(RegClass::get(RegType::vgpr, 2 * num_components)); in expand_vector()
443 RegClass src_rc = RegClass::get(RegType::vgpr, component_bytes); in expand_vector()
444 RegClass dst_rc = RegClass::get(dst.type(), component_bytes); in expand_vector()
563 RegClass rc = RegClass(RegType::vgpr, component_size).as_subdword(); in byte_align_vector()
582 vec = bld.pseudo(aco_opcode::p_as_uniform, bld.def(RegClass(RegType::sgpr, vec.size())), vec); in byte_align_vector()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 33 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
35 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass() argument
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
88 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
91 if (!RegClass) { in constrainOperandRegClass()
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
232 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 552 /// RegClass - This is the register class associated with this type. For
554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
660 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
668 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
[all …]
|
| D | X86FrameLowering.cpp | 586 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInline() local
588 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
590 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
592 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
594 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
596 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
598 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
600 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
602 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
604 : MRI.createVirtualRegister(RegClass); in emitStackProbeInline()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/ |
| D | AVRInstPrinter.cpp | 107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
109 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
106 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
109 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
117 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
122 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
610 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
611 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
614 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
|
| D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
98 switch (RegClass->getID()) { in maybeRewriteToFallthrough()
120 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTypes.h | 36 enum RegClass : uint8_t { enum
46 static_assert(RC_Target == static_cast<RegClass>(IceType_NUM),
86 const char *regClassString(RegClass C);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; variable
74 const RCInfo &RCI = RegClass[RC->getID()]; in get()
|
| D | RegisterScavenging.h | 166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
168 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
|
| /third_party/node/deps/v8/src/wasm/baseline/ |
| D | liftoff-register.h | 22 enum RegClass : uint8_t { enum
56 static inline constexpr RegClass reg_class_for(ValueKind kind) { in reg_class_for()
174 static LiftoffRegister from_code(RegClass rc, int code) { in from_code()
187 static LiftoffRegister from_external_code(RegClass rc, ValueKind kind, in from_external_code()
289 constexpr RegClass reg_class() const { in reg_class()
512 static constexpr LiftoffRegList GetCacheRegList(RegClass rc) { in GetCacheRegList()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 48 const TargetRegisterClass &RegClass);
63 const TargetRegisterClass &RegClass,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
92 RCInfo &RCI = RegClass[RC->getID()]; in compute()
|
| D | MachineRegisterInfo.cpp | 158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
160 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
166 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMachineCFGStructurizer.cpp | 1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1935 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1936 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2002 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2062 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2063 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2176 const TargetRegisterClass *RegClass = in createEntryPHI() local
2178 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass); in createEntryPHI()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 483 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
664 RegClass->contains(FrameReg))) { in rewriteT2FrameIndex()
668 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
705 RegClass->contains(FrameReg)); in rewriteT2FrameIndex()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 119 #define DECODE_OPERAND_REG(RegClass) \ argument
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
541 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst()
564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; in convertMIMGInst()
|