| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 112 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
113 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
115 WorklistMembers.set(RegIdx); in PutInWorklist()
116 Worklist.push_back(RegIdx); in PutInWorklist()
363 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
364 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
365 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
496 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
497 unsigned Reg = Register::index2VirtReg(RegIdx); in runOnce()
500 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
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| D | SplitKit.cpp | 456 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
463 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
472 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); in defValue()
493 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { in forceRecompute() argument
494 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute()
506 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); in forceRecompute()
540 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
553 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); in buildCopy()
627 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument
633 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
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| D | SplitKit.h | 343 LiveRangeCalc &getLRCalc(unsigned RegIdx) { in getLRCalc() argument
344 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; in getLRCalc()
369 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx,
376 void forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI);
384 VNInfo *defFromParent(unsigned RegIdx,
436 bool Late, unsigned RegIdx);
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| D | LiveVariables.cpp | 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { in getVarInfo() argument
86 assert(Register::isVirtualRegister(RegIdx) && in getVarInfo()
88 VirtRegInfo.grow(RegIdx); in getVarInfo()
89 return VirtRegInfo[RegIdx]; in getVarInfo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.cpp | 203 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
208 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
209 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
249 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
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| D | ARMISelLowering.cpp | 4037 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); in LowerFormalArguments() local
4038 if (RegIdx != array_lengthof(GPRArgRegs)) in LowerFormalArguments()
4039 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 863 struct RegIdxOp RegIdx; member
878 Op->RegIdx.Index = Index; in CreateReg()
879 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
880 Op->RegIdx.Kind = RegKind; in CreateReg()
881 Op->RegIdx.Tok.Data = Str.data(); in CreateReg()
882 Op->RegIdx.Tok.Length = Str.size(); in CreateReg()
892 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
893 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
895 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
901 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 115 unsigned RegIdx = ByteNumber / BytesPerReg; in PrintAsmOperand() local
116 assert(RegIdx < NumOpRegs && "Multibyte index out of range."); in PrintAsmOperand()
118 Reg = MI->getOperand(OpNum + RegIdx).getReg(); in PrintAsmOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 517 int RegIdx = mapRegToGPRIndex(LI.PhysReg); in runOnMachineFunction() local
518 if (RegIdx >= 0) in runOnMachineFunction()
519 LOHInfos[RegIdx].OneUser = true; in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg()
79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); in getMSACtrlReg()
842 SDValue RegIdx = Node->getOperand(2); in trySelect() local
844 getMSACtrlReg(RegIdx), MVT::i32); in trySelect()
875 SDValue RegIdx = Node->getOperand(2); in trySelect() local
878 getMSACtrlReg(RegIdx), Value); in trySelect()
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| D | MipsSEISelDAGToDAG.h | 35 unsigned getMSACtrlReg(const SDValue RegIdx) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | LiveVariables.h | 273 VarInfo &getVarInfo(unsigned RegIdx);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 2244 unsigned RegIdx = Log2_32(RegBytes); in canHardenRegister() local
2245 assert(RegIdx < 4 && "Unsupported register size"); in canHardenRegister()
2257 if (RC == NOREXRegClasses[RegIdx]) in canHardenRegister()
2263 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
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| D | X86FastISel.cpp | 2644 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall() local
2645 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx); in fastLowerIntrinsicCall()
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| D | X86ISelLowering.cpp | 32200 for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) { in EmitSjLjDispatchBlock() local
32201 unsigned Reg = SavedRegs[RegIdx]; in EmitSjLjDispatchBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1522 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_RISCV() local
1524 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) in CC_RISCV()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2129 unsigned RegIdx = RegNum / AlignSize; in getRegularReg() local
2136 if (RegIdx >= RC.getNumRegs()) in getRegularReg()
2139 return RC.getRegister(RegIdx); in getRegularReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1666 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); in allocateVGPR32Input() local
1667 if (RegIdx == ArgVGPRs.size()) { in allocateVGPR32Input()
1674 unsigned Reg = ArgVGPRs[RegIdx]; in allocateVGPR32Input()
1688 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); in allocateSGPR32InputImpl() local
1689 if (RegIdx == ArgSGPRs.size()) in allocateSGPR32InputImpl()
1692 unsigned Reg = ArgSGPRs[RegIdx]; in allocateSGPR32InputImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6647 unsigned RegIdx = 3; in shouldOmitPredicateOperand() local
6655 RegIdx = 4; in shouldOmitPredicateOperand()
6657 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
6659 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
6661 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
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