Searched refs:RegLo (Results 1 – 6 of 6) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVISelLowering.cpp | 2178 Register RegLo = VA.getLocReg(); in LowerCall() local 2179 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall() 2181 if (RegLo == RISCV::X17) { in LowerCall() 2191 assert(RegLo < RISCV::X31 && "Invalid register pair"); in LowerCall() 2192 Register RegHigh = RegLo + 1; in LowerCall() 2420 Register RegLo = VA.getLocReg(); in LowerReturn() local 2421 assert(RegLo < RISCV::X31 && "Invalid register pair"); in LowerReturn() 2422 Register RegHi = RegLo + 1; in LowerReturn() 2424 if (STI.isRegisterReservedByUser(RegLo) || in LowerReturn() 2430 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
D | AMDGPUAsmParser.cpp | 2144 int64_t RegLo, RegHi; in ParseRegRange() local 2148 if (!parseExpr(RegLo)) in ParseRegRange() 2155 RegHi = RegLo; in ParseRegRange() 2161 if (!isUInt<32>(RegLo) || !isUInt<32>(RegHi) || RegLo > RegHi) in ParseRegRange() 2164 Num = static_cast<unsigned>(RegLo); in ParseRegRange() 2165 Width = (RegHi - RegLo) + 1; in ParseRegRange()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local 1041 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
D | IceTargetLoweringMIPS32.cpp | 3836 Variable *RegHi, *RegLo; in lowerCast() local 3840 RegLo = legalizeToReg(Ctx->getConstantInt32(Lower32Bits)); in lowerCast() 3842 _mov(Dest, RegHi, RegLo); in lowerCast() 3845 auto *RegLo = legalizeToReg(loOperand(Var64On32)); in lowerCast() local 3847 _mov(Dest, RegHi, RegLo); in lowerCast()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 1515 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local 1525 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo) in expandPostRAPseudo() 1526 .addReg(RegLo) in expandPostRAPseudo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 3585 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local 3587 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32); in LowerFormalArguments_32SVR4()
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