| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 152 static const char *stripRegisterPrefix(const char *RegName) { in stripRegisterPrefix() argument
153 switch (RegName[0]) { in stripRegisterPrefix()
158 if (RegName[1] == 's') in stripRegisterPrefix()
159 return RegName + 2; in stripRegisterPrefix()
160 return RegName + 1; in stripRegisterPrefix()
161 case 'c': if (RegName[1] == 'r') return RegName + 2; in stripRegisterPrefix()
164 return RegName; in stripRegisterPrefix()
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| D | PPCAsmPrinter.cpp | 207 const char *RegName = PPCInstPrinter::getRegisterName(MO.getReg()); in printOperand() local
212 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); in printOperand()
213 O << RegName; in printOperand()
277 const char *RegName; in PrintAsmOperand() local
278 RegName = PPCInstPrinter::getRegisterName(Reg); in PrintAsmOperand()
279 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); in PrintAsmOperand()
280 O << RegName; in PrintAsmOperand()
303 const char *RegName = "r0"; in PrintAsmMemoryOperand() local
305 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); in PrintAsmMemoryOperand()
306 O << RegName << ", "; in PrintAsmMemoryOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCInstPrinter.cpp | 51 const char *RegName = getRegisterName(RegNo); in printRegName() local
52 if (RegName[0] == 'q' /* QPX */) { in printRegName()
56 std::string RN(RegName); in printRegName()
64 OS << RegName; in printRegName()
492 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { in showRegistersWithPercentPrefix()
496 switch (RegName[0]) { in showRegistersWithPercentPrefix()
547 const char *RegName; in printOperand() local
548 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); in printOperand()
549 if (RegName == nullptr) in printOperand()
550 RegName = getRegisterName(Reg); in printOperand()
[all …]
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| D | PPCInstPrinter.h | 24 bool showRegistersWithPercentPrefix(const char *RegName) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 75 Register VETargetLowering::getRegisterByName(const char *RegName, LLT VT, in getRegisterByName() argument
77 Register Reg = StringSwitch<Register>(RegName) in getRegisterByName()
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| D | VEISelLowering.h | 38 Register getRegisterByName(const char *RegName, LLT VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/MIRParser/ |
| D | MIParser.h | 103 bool getRegisterByName(StringRef RegName, unsigned &Reg);
182 VRegInfo &getVRegInfoNamed(StringRef RegName);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetMachine.cpp | 1025 auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) { in parseMachineFunctionInfo() argument
1026 if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) { in parseMachineFunctionInfo()
1027 SourceRange = RegName.SourceRange; in parseMachineFunctionInfo()
1034 auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) { in parseMachineFunctionInfo() argument
1039 RegName.Value.size(), SourceMgr::DK_Error, in parseMachineFunctionInfo()
1040 "incorrect register class for field", RegName.Value, in parseMachineFunctionInfo()
1042 SourceRange = RegName.SourceRange; in parseMachineFunctionInfo()
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| D | SIISelLowering.h | 333 Register getRegisterByName(const char* RegName, LLT VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 152 void splitToClassAndName(const std::string &RegName, std::string *SplitRegClass, in splitToClassAndName() argument
156 size_t Pos = RegName.find(Separator); in splitToClassAndName()
159 *SplitRegName = RegName; in splitToClassAndName()
161 *SplitRegClass = RegName.substr(0, Pos); in splitToClassAndName()
162 *SplitRegName = RegName.substr(Pos + SeparatorWidth); in splitToClassAndName()
224 for (const auto &RegName : BadRegNames) in filterTypeToRegisterSet() local
225 StrBuf << " " << RegName; in filterTypeToRegisterSet()
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| D | IceAssemblerMIPS32.cpp | 164 const char *RegName, const char *InstName) { in encodeRegister() argument
168 RegName); in encodeRegister()
172 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
174 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
177 IValueT encodeFPRegister(const Operand *OpReg, const char *RegName, in encodeFPRegister() argument
179 return encodeRegister(OpReg, WantFPRegs, RegName, InstName); in encodeFPRegister()
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| D | IceAssemblerARM32.cpp | 541 const char *RegName, const char *InstName) { in encodeRegister() argument
545 RegName); in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
551 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister() argument
556 return encodeRegister(OpReg, WantSRegs, RegName, InstName); in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister() argument
561 return encodeRegister(OpReg, WantDRegs, RegName, InstName); in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister() argument
566 return encodeRegister(OpReg, WantQRegs, RegName, InstName); in encodeQRegister()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/DWARF/ |
| D | DWARFExpression.cpp | 224 if (const char *RegName = MRI->getName(*LLVMRegNum)) { in prettyPrintRegisterOp() local
227 OS << format(" %s%+" PRId64, RegName, Operands[OpNum]); in prettyPrintRegisterOp()
229 OS << ' ' << RegName; in prettyPrintRegisterOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 575 if (const char *RegName = getRegisterName(Key.getUInt())) { in toString() local
578 KeyName += RegName; in toString()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/AsmParser/ |
| D | AVRAsmParser.cpp | 704 std::ostringstream RegName; in validateTargetOperandClass() local
705 RegName << "r" << RegNum; in validateTargetOperandClass()
706 RegNum = MatchRegisterName(RegName.str().c_str()); in validateTargetOperandClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.h | 93 Register getRegisterByName(const char *RegName, LLT VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 128 Register getRegisterByName(const char* RegName, LLT VT,
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| D | AVRISelLowering.cpp | 2008 Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, in getRegisterByName() argument
2013 Reg = StringSwitch<unsigned>(RegName) in getRegisterByName()
2028 Reg = StringSwitch<unsigned>(RegName) in getRegisterByName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.h | 101 Register getRegisterByName(const char* RegName, LLT VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.h | 154 Register getRegisterByName(const char *RegName, LLT VT,
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| D | RISCVISelLowering.cpp | 2910 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT, in getRegisterByName() argument
2912 Register Reg = MatchRegisterAltName(RegName); in getRegisterByName()
2914 Reg = MatchRegisterName(RegName); in getRegisterByName()
2917 Twine("Invalid register name \"" + StringRef(RegName) + "\".")); in getRegisterByName()
2921 StringRef(RegName) + "\".")); in getRegisterByName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1175 StringRef RegName = Tok.getString(); in ParseRegister() local
1178 "register %" + RegName + " is only available in 64-bit mode", in ParseRegister()
1372 std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI"; in VerifyAndAdjustOperands() local
1375 "memory operand is only for determining the size, " + RegName + in VerifyAndAdjustOperands()
3081 StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2); in validateInstruction() local
3085 "source register '" + RegName + "' implicitly denotes '" + in validateInstruction()
3086 RegName.take_front(3) + Twine(GroupStart) + "' to '" + in validateInstruction()
3087 RegName.take_front(3) + Twine(GroupEnd) + in validateInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 124 bool PerTargetMIParsingState::getRegisterByName(StringRef RegName, in getRegisterByName() argument
127 auto RegInfo = Names2Regs.find(RegName); in getRegisterByName()
335 VRegInfo &PerFunctionMIParsingState::getVRegInfoNamed(StringRef RegName) { in getVRegInfoNamed() argument
336 assert(RegName != "" && "Expected named reg."); in getVRegInfoNamed()
338 auto I = VRegInfosNamed.insert(std::make_pair(RegName.str(), nullptr)); in getVRegInfoNamed()
341 Info->VReg = MF.getRegInfo().createIncompleteVirtualRegister(RegName); in getVRegInfoNamed()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 233 Register getRegisterByName(const char* RegName, LLT VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3712 auto RegName = [](unsigned Reg) { in print() local
3727 OS << "<ccout " << RegName(getReg()) << ">"; in print()
3770 OS << " base:" << RegName(Memory.BaseRegNum); in print()
3775 << RegName(Memory.OffsetRegNum); in print()
3786 << RegName(PostIdxReg.RegNum); in print()
3802 OS << "<register " << RegName(getReg()) << ">"; in print()
3809 OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " " in print()
3811 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
3814 OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " " in print()
3843 OS << RegName(*I); in print()
[all …]
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