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Searched refs:RegType (Results 1 – 25 of 30) sorted by relevance

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/third_party/node/deps/v8/src/codegen/
Dregister-base.h66 template <typename RegType,
67 typename = decltype(RegisterName(std::declval<RegType>()))>
68 inline std::ostream& operator<<(std::ostream& os, RegType reg) {
75 #define DEFINE_REGISTER_NAMES(RegType, LIST) \ argument
76 inline const char* RegisterName(RegType reg) { \
78 STATIC_ASSERT(arraysize(Names) == RegType::kNumRegisters); \
/third_party/mesa3d/src/amd/compiler/
Daco_validate.cpp323 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
326 check(instr->definitions[0].getTemp().type() == RegType::vgpr, in validate_ir()
337 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
340 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
347 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr), in validate_ir()
349 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
357 check(i != 2 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
360 check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
365 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) { in validate_ir()
385 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
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Daco_instruction_selection_setup.cpp241 get_reg_class(isel_context* ctx, RegType type, unsigned components, unsigned bitsize) in get_reg_class()
244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
479 RegType type = in init_context()
480 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr; in init_context()
544 case nir_op_sdot_2x16_iadd_sat: type = RegType::vgpr; break; in init_context()
575 type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type; in init_context()
579 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr) in init_context()
580 type = RegType::vgpr; in init_context()
593 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
601 RegType type = RegType::sgpr; in init_context()
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Daco_spill.cpp205 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in next_uses_per_block()
415 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in update_local_next_uses()
529 RegType type = RegType::vgpr; in init_live_in_vars()
532 if (type == RegType::vgpr && loop_demand.vgpr <= ctx.target_pressure.vgpr) in init_live_in_vars()
533 type = RegType::sgpr; in init_live_in_vars()
535 if (type == RegType::sgpr && loop_demand.sgpr <= ctx.target_pressure.sgpr) in init_live_in_vars()
544 (ctx.remat.count(pair.first) && type == RegType::sgpr)) && in init_live_in_vars()
553 if (type == RegType::sgpr) in init_live_in_vars()
555 type = RegType::sgpr; in init_live_in_vars()
581 type = reg_pressure.vgpr > ctx.target_pressure.vgpr ? RegType::vgpr : RegType::sgpr; in init_live_in_vars()
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Daco_lower_to_cssa.cpp103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) { in collect_parallelcopies()
173 idom = b.regClass().type() == RegType::vgpr ? ctx.program->blocks[idom].logical_idom in dominates()
197 std::vector<uint32_t>& preds = var.type() == RegType::vgpr in intersects()
351 pred = copy.op.regClass().type() == RegType::vgpr ? ctx.program->blocks[pred].logical_idom in try_coalesce_copy()
387 emit_copies_block(Builder& bld, std::map<uint32_t, ltg_node>& ltg, RegType type) in emit_copies_block()
466 bool is_vgpr = cp.def.regClass().type() == RegType::vgpr; in emit_parallelcopies()
492 emit_copies_block(bld, ltg, RegType::vgpr); in emit_parallelcopies()
500 emit_copies_block(bld, ltg, RegType::sgpr); in emit_parallelcopies()
Daco_instruction_selection.cpp274 if (val.type() == RegType::sgpr) in as_vgpr()
275 return bld.copy(bld.def(RegType::vgpr, val.size()), val); in as_vgpr()
276 assert(val.type() == RegType::vgpr); in as_vgpr()
363 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr); in emit_extract_vector()
390 if (vec_src.type() == RegType::sgpr) { in emit_split_vector()
396 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword(); in emit_split_vector()
418 assert(vec_src.type() == RegType::vgpr); in expand_vector()
421 if (dst.type() == RegType::sgpr && num_components > dst.size()) { in expand_vector()
422 Temp tmp_dst = bld.tmp(RegClass::get(RegType::vgpr, 2 * num_components)); in expand_vector()
435 if (dst.type() == RegType::sgpr) in expand_vector()
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Daco_reduce_assign.cpp60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
Daco_ir.h301 enum class RegType { enum
340 constexpr RegClass(RegType type, unsigned size) in RegClass()
341 : rc((RC)((type == RegType::vgpr ? 1 << 5 : 0) | size)) in RegClass()
347 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; } in type()
357 static constexpr RegClass get(RegType type, unsigned bytes) in get()
359 if (type == RegType::sgpr) { in get()
370 return get(RegType::vgpr, bytes).as_linear(); in resize()
416 constexpr RegType type() const noexcept { return regClass().type(); } in type()
824 constexpr bool isOfType(RegType type) const noexcept in isOfType()
1861 if (t.type() == RegType::sgpr)
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Daco_live_var_analysis.cpp98 instr->operands[2].regClass().type() == RegType::sgpr) in instr_needs_vcc()
219 assert(definition.getTemp().type() == RegType::sgpr); in process_live_temps_per_block()
265 if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr) { in process_live_temps_per_block()
268 assert(operand.getTemp().type() == RegType::sgpr); in process_live_temps_per_block()
Daco_lower_to_hw_instr.cpp391 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
431 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
815 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) { in emit_reduction()
828 if (dst.regClass().type() == RegType::sgpr) { in emit_reduction()
867 assert(input_data.regClass().type() == RegType::vgpr); in emit_gfx10_wave64_bpermute()
936 assert(input.regClass().type() == RegType::vgpr); in emit_gfx6_bpermute()
980 if (ctx->program->gfx_level < GFX10 && src.def.regClass().type() == RegType::vgpr) in split_copy()
982 unsigned max_align = src.def.regClass().type() == RegType::vgpr ? 4 : 16; in split_copy()
1247 Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
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Daco_register_allocation.cpp178 if (rc.type() == RegType::vgpr) { in get_stride()
193 get_reg_bounds(Program* program, RegType type) in get_reg_bounds()
195 if (type == RegType::vgpr) { in get_reg_bounds()
420 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr); in print_regs()
749 if (rc.type() == RegType::vgpr) { in adjust_max_used_regs()
896 (rc.type() == RegType::vgpr) ? (256 + ctx.max_used_vgpr) : ctx.max_used_sgpr; in get_reg_simple()
1400 if (rc.type() == RegType::sgpr && reg % get_stride(rc) != 0) in get_reg_specified()
1407 bool is_vcc = rc.type() == RegType::sgpr && vcc_win.contains(reg_win) && ctx.program->needs_vcc; in get_reg_specified()
1427 increase_register_file(ra_ctx& ctx, RegType type) in increase_register_file()
1429 if (type == RegType::vgpr && ctx.program->max_reg_demand.vgpr < ctx.vgpr_limit) { in increase_register_file()
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Daco_optimizer.cpp543 [](const Definition& def) { return def.regClass().type() == RegType::vgpr; }); in pseudo_propagate_temp()
546 if (temp.type() == RegType::vgpr && !vgpr) in pseudo_propagate_temp()
564 if (temp.type() == RegType::sgpr && !can_accept_sgpr) in pseudo_propagate_temp()
568 if (temp.type() == RegType::sgpr && !can_accept_sgpr) in pseudo_propagate_temp()
640 return op.isTemp() && op.getTemp().type() == RegType::vgpr; in is_operand_vgpr()
708 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) { in check_vop3_operands()
1078 (tmp.type() == RegType::vgpr || ctx.program->gfx_level >= GFX9)) { in can_apply_extract()
1134 (tmp.type() == RegType::vgpr || ctx.program->gfx_level >= GFX9)) { in apply_extract()
1169 if (info.is_extract() && (info.instr->operands[0].getTemp().type() == RegType::vgpr || in check_sdwa_extract()
1170 op.getTemp().type() == RegType::sgpr)) { in check_sdwa_extract()
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Daco_ir.cpp230 if (gfx_level < GFX9 && !instr->operands[i].isOfType(RegType::vgpr)) in can_use_SDWA()
241 if (gfx_level < GFX9 && !instr->operands[0].isOfType(RegType::vgpr)) in can_use_SDWA()
302 if (instr->definitions[0].getTemp().type() == RegType::sgpr && gfx_level == GFX8) in convert_to_SDWA()
343 if (instr->operands.size() > 1 && !instr->operands[1].isOfType(RegType::vgpr)) in can_use_DPP()
586 if (def.getTemp().type() == RegType::vgpr) in needs_exec_mask()
762 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr)) in can_swap_operands()
Daco_insert_NOPs.cpp418 if (def.regClass().type() != RegType::sgpr) { in handle_instruction_gfx6()
449 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr) in handle_instruction_gfx6()
510 if (def.regClass().type() == RegType::sgpr) { in handle_instruction_gfx6()
548 instr->operands[1].regClass().type() == RegType::vgpr && in handle_instruction_gfx6()
628 { return def.getTemp().type() == RegType::sgpr; }); in instr_writes_sgpr()
Daco_lower_phis.cpp325 assert(phi_src.regClass().type() == RegType::sgpr); in lower_subdword_phis()
326 Temp tmp = bld.tmp(RegClass(RegType::vgpr, phi_src.size())); in lower_subdword_phis()
Daco_optimizer_postRA.cpp123 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255); in save_reg_writes()
124 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256); in save_reg_writes()
Daco_print_ir.cpp94 } else if (rc.type() == RegType::sgpr) { in print_reg_class()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerX8664.h886 template <typename RegType, typename RmType>
887 inline void emitXmmRegisterOperand(RegType reg, RmType rm);
933 template <typename RegType> GPRRegister gprEncoding(const RegType Reg) { in gprEncoding()
937 template <typename RegType>
938 bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) { in is8BitRegisterRequiringRex()
940 std::is_same<typename std::decay<RegType>::type, ByteRegister>::value || in is8BitRegisterRequiringRex()
941 std::is_same<typename std::decay<RegType>::type, GPRRegister>::value; in is8BitRegisterRequiringRex()
962 template <typename RegType, typename RmType>
963 void assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
985 template <typename RegType, typename RmType>
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DIceAssemblerX8632.h890 template <typename RegType, typename RmType>
891 inline void emitXmmRegisterOperand(RegType reg, RmType rm);
935 template <typename RegType> GPRRegister gprEncoding(const RegType Reg) { in gprEncoding()
958 template <typename RegType, typename RmType>
959 inline void AssemblerX8632::emitXmmRegisterOperand(RegType reg, RmType rm) { in emitXmmRegisterOperand()
DIceTargetLoweringMIPS32.cpp1629 Type RegType; in addProlog() local
1631 RegType = IceType_f32; in addProlog()
1633 RegType = IceType_i32; in addProlog()
1634 auto *PhysicalRegister = makeReg(RegType, Var->getRegNum()); in addProlog()
1635 StackOffset -= typeWidthInBytesOnStack(RegType); in addProlog()
1638 Func, RegType, SP, in addProlog()
1753 Type RegType; in addEpilog() local
1755 RegType = IceType_f32; in addEpilog()
1757 RegType = IceType_i32; in addEpilog()
1758 auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum()); in addEpilog()
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/third_party/mesa3d/src/amd/compiler/tests/
Dhelpers.cpp114 RegType type = input_spec[0] == 'v' ? RegType::vgpr : RegType::sgpr; in setup_cs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5406 string kind2, RegisterOperand RegType,
5409 BaseSIMDThreeSameVectorTied<Q, U, 0b100, 0b10010, RegType, asm, kind1,
5410 [(set (AccumType RegType:$dst),
5411 (OpNode (AccumType RegType:$Rd),
5412 (InputType RegType:$Rn),
5413 (InputType RegType:$Rm)))]> {
5428 string kind2, RegisterOperand RegType,
5431 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
5432 [(set (AccumType RegType:$dst),
5433 (OpNode (AccumType RegType:$Rd),
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/third_party/node/deps/v8/src/codegen/mips/
Dassembler-mips.h1735 template <typename RegType>
1736 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t,
Dassembler-mips.cc1301 template <typename RegType>
1303 RegType t, MSARegister ws, MSARegister wd) { in GenInstrMsa3R()
/third_party/node/deps/v8/src/codegen/mips64/
Dassembler-mips64.h1771 template <typename RegType>
1772 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t,

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