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Searched refs:RegUnit (Results 1 – 22 of 22) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterPressure.cpp100 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
108 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
155 void RegPressureTracker::increaseRegPressure(unsigned RegUnit, in increaseRegPressure() argument
161 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
170 void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, in decreaseRegPressure() argument
173 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
363 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
364 if (Register::isVirtualRegister(RegUnit) in initLiveThru()
365 && !RPTracker.hasUntiedDef(RegUnit)) in initLiveThru()
366 increaseSetPressure(LiveThruPressure, *MRI, RegUnit, in initLiveThru()
[all …]
DLiveRegMatrix.cpp179 unsigned RegUnit) { in query() argument
180 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
DMachineCopyPropagation.cpp176 MachineInstr *findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI, in findCopyForUnit() argument
178 auto CI = Copies.find(RegUnit); in findCopyForUnit()
186 MachineInstr *findCopyDefViaUnit(unsigned RegUnit, in findCopyDefViaUnit() argument
188 auto CI = Copies.find(RegUnit); in findCopyDefViaUnit()
DMachineTraceMetrics.cpp1144 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); in computeInstrHeights()
1145 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@' in computeInstrHeights()
DMachineScheduler.cpp1101 unsigned Reg = P.RegUnit; in updatePressureDiffs()
1326 unsigned Reg = P.RegUnit; in computeCyclicCriticalPath()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterPressure.h40 unsigned RegUnit; ///< Virtual register or register unit. member
43 RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
44 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
160 void addPressureChange(unsigned RegUnit, bool IsDec,
306 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in insert()
319 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in erase()
551 void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
553 void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
564 LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
565 LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
[all …]
DMachineRegisterInfo.h622 PSetIterator getPressureSets(unsigned RegUnit) const;
1177 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1179 if (Register::isVirtualRegister(RegUnit)) { in PSetIterator()
1180 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1185 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1186 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1207 getPressureSets(unsigned RegUnit) const { in getPressureSets() argument
1208 return PSetIterator(RegUnit, this); in getPressureSets()
DMachineTraceMetrics.h76 unsigned RegUnit; member
81 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
83 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
DTargetRegisterInfo.h397 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit() argument
399 if (*Units == RegUnit) in hasRegUnit()
744 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
764 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
DLiveRegMatrix.h150 LiveIntervalUnion::Query &query(const LiveRange &LR, unsigned RegUnit);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp243 return RM.RegUnit == Reg; in collectVirtualRegUses()
324 auto LiveMask = LiveRegs[U.RegUnit]; in recede()
325 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI); in recede()
346 auto &LiveMask = LiveRegs[U.RegUnit]; in recede()
349 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI); in recede()
DSIMachineScheduler.h474 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
482 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
DSIWholeQuadMode.cpp287 for (MCRegUnitIterator RegUnit(Reg, TRI); RegUnit.isValid(); ++RegUnit) { in markInstructionUses() local
288 LiveRange &LR = LIS->getRegUnit(*RegUnit); in markInstructionUses()
DSIRegisterInfo.h250 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
DSIMachineScheduler.cpp351 if (Register::isVirtualRegister(RegMaskPair.RegUnit)) in initRegPressure()
352 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
378 unsigned Reg = RegMaskPair.RegUnit; in initRegPressure()
DSIRegisterInfo.cpp1751 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
1754 if (hasRegUnit(AMDGPU::M0, RegUnit)) in getRegUnitPressureSets()
1756 return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCRegisterInfo.h745 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
746 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
747 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
748 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc3849 unsigned getRegUnitWeight(unsigned RegUnit) const override;
3854 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5549 getRegUnitWeight(unsigned RegUnit) const {
5550 assert(RegUnit < 171 && "invalid register unit");
5636 getRegUnitPressureSets(unsigned RegUnit) const {
5637 assert(RegUnit < 171 && "invalid register unit");
5640 return &RCSetsTable[RUSetStartTable[RegUnit]];
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc3815 unsigned getRegUnitWeight(unsigned RegUnit) const override;
3820 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
7225 getRegUnitWeight(unsigned RegUnit) const {
7226 assert(RegUnit < 321 && "invalid register unit");
7322 getRegUnitPressureSets(unsigned RegUnit) const {
7323 assert(RegUnit < 321 && "invalid register unit");
7326 return &RCSetsTable[RUSetStartTable[RegUnit]];
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc4321 unsigned getRegUnitWeight(unsigned RegUnit) const override;
4326 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
9731 getRegUnitWeight(unsigned RegUnit) const {
9732 assert(RegUnit < 164 && "invalid register unit");
9877 getRegUnitPressureSets(unsigned RegUnit) const {
9878 assert(RegUnit < 164 && "invalid register unit");
9881 return &RCSetsTable[RUSetStartTable[RegUnit]];
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc3587 unsigned getRegUnitWeight(unsigned RegUnit) const override;
3592 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
15784 getRegUnitWeight(unsigned RegUnit) const {
15785 assert(RegUnit < 83 && "invalid register unit");
15788 return RUWeightTable[RegUnit];
15925 getRegUnitPressureSets(unsigned RegUnit) const {
15926 assert(RegUnit < 83 && "invalid register unit");
15929 return &RCSetsTable[RUSetStartTable[RegUnit]];
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc5035 unsigned getRegUnitWeight(unsigned RegUnit) const override;
5040 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
20182 getRegUnitWeight(unsigned RegUnit) const {
20183 assert(RegUnit < 115 && "invalid register unit");
20330 getRegUnitPressureSets(unsigned RegUnit) const {
20331 assert(RegUnit < 115 && "invalid register unit");
20334 return &RCSetsTable[RUSetStartTable[RegUnit]];