| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 1028 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
1030 let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
1034 # RegWidth # ", AArch64::ZPRRegClassID, "
1039 let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
1045 int RegWidth, int Scale, string Suffix = "">
1048 !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
1053 # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
1056 foreach RegWidth = [32, 64] in {
1058 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1059 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
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| D | AArch64ISelDAGToDAG.cpp | 262 template<unsigned RegWidth>
264 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
2662 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
2698 if (FBits == 0 || FBits > RegWidth) return false; in SelectCVTFixedPosOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 801 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias() argument
802 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias()
809 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
810 if (RegWidth == 32) in isMOVZMovAlias()
820 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias() argument
822 if (isAnyMOVZMovAlias(Value, RegWidth)) in isMOVNMovAlias()
826 if (RegWidth == 32) in isMOVNMovAlias()
829 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
832 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias() argument
833 if (isAnyMOVZMovAlias(Value, RegWidth)) in isAnyMOVWMovAlias()
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| D | AArch64InstPrinter.cpp | 238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
245 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
255 if (RegWidth == 32) in printInst()
258 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { in printInst()
260 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
271 MI->getOperand(2).getImm(), RegWidth); in printInst()
272 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { in printInst()
274 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonTargetTransformInfo.cpp | 166 unsigned RegWidth = getRegisterBitWidth(true); in getMemoryOpCost() local
167 assert(RegWidth && "Non-zero vector register width expected"); in getMemoryOpCost()
169 if (VecWidth % RegWidth == 0) in getMemoryOpCost()
170 return VecWidth / RegWidth; in getMemoryOpCost()
172 const Align RegAlign(RegWidth / 8); in getMemoryOpCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 987 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister() argument
989 case IS_SGPR: usesSgprAt(DwordRegIndex + RegWidth - 1); break; in usesRegister()
991 case IS_VGPR: usesVgprAt(DwordRegIndex + RegWidth - 1); break; in usesRegister()
1063 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1066 unsigned& RegNum, unsigned& RegWidth);
1069 unsigned &RegWidth);
1072 unsigned &RegWidth);
1075 unsigned &RegWidth);
1079 unsigned RegWidth);
1086 unsigned RegWidth);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 968 template<int RegWidth, int Shift>
976 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
979 template<int RegWidth, int Shift>
987 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
4550 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4553 RegWidth = 64; in MatchAndEmitInstruction()
4555 RegWidth = 32; in MatchAndEmitInstruction()
4557 if (LSB >= RegWidth) in MatchAndEmitInstruction()
4560 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
4565 if (RegWidth == 32) in MatchAndEmitInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1325 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
1326 return (BitWidth + RegWidth - 1) / RegWidth; in getNumRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 6351 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
6353 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchInst()
6362 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchInst()
6380 NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth); in optimizeSwitchInst()
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