| /third_party/node/deps/v8/src/codegen/ |
| D | cpu-features.h | 21 SAHF, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 548 SAHF, enumerator
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| D | X86.td | 235 "Support LAHF and SAHF instructions">;
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| D | X86ScheduleBdVer2.td | 525 def : InstRW<[PdWriteSAHF], (instrs SAHF)>;
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| D | X86InstrInfo.td | 155 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
1791 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
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| D | X86ISelLowering.cpp | 20920 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); in ConvertCmpIfNecessary()
22027 Opc == X86ISD::SAHF) in isX86LogicalCmp()
29807 case X86ISD::SAHF: return "X86ISD::SAHF"; in getTargetNodeName()
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| /third_party/node/deps/v8/src/codegen/x64/ |
| D | assembler-x64.cc | 106 if (cpu.has_sahf() && FLAG_enable_sahf) SetSupported(SAHF); in ProbeImpl()
151 CpuFeatures::IsSupported(SAHF), CpuFeatures::IsSupported(AVX), in PrintFeatures()
2692 DCHECK(IsEnabled(SAHF)); in sahf()
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| /third_party/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 600 #define SAHF CHOICE(sahf, sahf, sahf) macro
1313 #define SAHF sahf macro
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| /third_party/rust/crates/memchr/bench/data/sliceslice/ |
| D | words.txt | 3578 SAHF
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| D | i386.txt | 616 SAHF
684 3-22 LAHF and SAHF
4184 The instructions LAHF and SAHF deal with five of the status flags, which
4191 SAHF (Store AH into Flags) transfers bits 7, 6, 4, 2, and 0 from AH into
4211 Figure 3-22. LAHF and SAHF
4218 LAHF LOADS FIVE FLAGS FROM THE FLAG REGISTER INTO REGISTER AH. SAHF
18966 SAHF Store AH into Flags
18970 9E SAHF 3 Store AH into flags SF ZF xx AF xx PF xx CF
18979 SAHF loads the flags listed above with values from the AH register,
20464 9 NOP Ĵ CBW CWD WAIT SAHF LAHF
[all …]
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| D | i386-notutf8.txt | 616 SAHF
684 3-22 LAHF and SAHF
4184 The instructions LAHF and SAHF deal with five of the status flags, which
4191 SAHF (Store AH into Flags) transfers bits 7, 6, 4, 2, and 0 from AH into
4211 Figure 3-22. LAHF and SAHF
4218 LAHF LOADS FIVE FLAGS FROM THE FLAG REGISTER INTO REGISTER AH. SAHF
18966 SAHF �� Store AH into Flags
18970 9E SAHF 3 Store AH into flags SF ZF xx AF xx PF xx CF
18979 SAHF loads the flags listed above with values from the AH register,
20464 …��������������������Ĵ CBW � CWD � � WAIT � � � SAHF � LAHF �
[all …]
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| /third_party/node/deps/v8/src/compiler/backend/x64/ |
| D | code-generator-x64.cc | 1850 if (CpuFeatures::IsSupported(SAHF)) { in AssembleArchInstruction()
1851 CpuFeatureScope sahf_scope(tasm(), SAHF); in AssembleArchInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 252 …{ "sahf", "Support LAHF and SAHF instructions", X86::FeatureLAHFSAHF, { { { 0x0ULL, 0x0ULL, 0x0ULL…
6702 {DBGFIELD("SAHF") 1, false, false, 3, 1, 3, 1, 0, 0}, // #1013
8079 {DBGFIELD("SAHF") 2, false, false, 79, 2, 3, 1, 0, 0}, // #1013
9456 {DBGFIELD("SAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #1013
10833 {DBGFIELD("SAHF") 1, false, false, 1, 1, 1, 1, 0, 0}, // #1013
12210 {DBGFIELD("SAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #1013
13587 {DBGFIELD("SAHF") 1, false, false, 1038, 3, 1, 1, 0, 0}, // #1013
14964 {DBGFIELD("SAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #1013
16341 {DBGFIELD("SAHF") 1, false, false, 188, 1, 1, 1, 0, 0}, // #1013
17718 {DBGFIELD("SAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #1013
[all …]
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| D | X86GenAsmWriter.inc | 4190 15646U, // SAHF
19441 0U, // SAHF
34692 0U, // SAHF
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| D | X86GenAsmWriter1.inc | 3899 12421U, // SAHF
19150 0U, // SAHF
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| D | X86GenDisassemblerTables.inc | 17459 /* SAHF */
76894 0x9db, /* SAHF */
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| D | X86GenAsmMatcher.inc | 10150 { 7011 /* sahf */, X86::SAHF, Convert_NoOperands, AMFBS_None, { }, },
24710 { 7011 /* sahf */, X86::SAHF, Convert_NoOperands, AMFBS_None, { }, },
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| D | X86GenInstrInfo.inc | 2538 SAHF = 2523,
16290 SAHF = 1013,
20223 …3, 0, 0x2780000001ULL, ImplicitList51, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2523 = SAHF
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