1 /**************************************************************************//**
2 * @file partition_ARMCM55.h
3 * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
4 * @version V1.0.0
5 * @date 20. March 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef PARTITION_ARMCM55_H
26 #define PARTITION_ARMCM55_H
27
28 /*
29 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
30 */
31
32 /*
33 // <e>Initialize Security Attribution Unit (SAU) CTRL register
34 */
35 #define SAU_INIT_CTRL 1
36
37 /*
38 // <q> Enable SAU
39 // <i> Value for SAU->CTRL register bit ENABLE
40 */
41 #define SAU_INIT_CTRL_ENABLE 1
42
43 /*
44 // <o> When SAU is disabled
45 // <0=> All Memory is Secure
46 // <1=> All Memory is Non-Secure
47 // <i> Value for SAU->CTRL register bit ALLNS
48 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
49 */
50 #define SAU_INIT_CTRL_ALLNS 0
51
52 /*
53 // </e>
54 */
55
56 /*
57 // <h>Initialize Security Attribution Unit (SAU) Address Regions
58 // <i>SAU configuration specifies regions to be one of:
59 // <i> - Secure and Non-Secure Callable
60 // <i> - Non-Secure
61 // <i>Note: All memory regions not configured by SAU are Secure
62 */
63 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
64
65 /*
66 // <e>Initialize SAU Region 0
67 // <i> Setup SAU Region 0 memory attributes
68 */
69 #define SAU_INIT_REGION0 1
70
71 /*
72 // <o>Start Address <0-0xFFFFFFE0>
73 */
74 #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
75
76 /*
77 // <o>End Address <0x1F-0xFFFFFFFF>
78 */
79 #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
80
81 /*
82 // <o>Region is
83 // <0=>Non-Secure
84 // <1=>Secure, Non-Secure Callable
85 */
86 #define SAU_INIT_NSC0 1
87 /*
88 // </e>
89 */
90
91 /*
92 // <e>Initialize SAU Region 1
93 // <i> Setup SAU Region 1 memory attributes
94 */
95 #define SAU_INIT_REGION1 1
96
97 /*
98 // <o>Start Address <0-0xFFFFFFE0>
99 */
100 #define SAU_INIT_START1 0x00200000
101
102 /*
103 // <o>End Address <0x1F-0xFFFFFFFF>
104 */
105 #define SAU_INIT_END1 0x003FFFFF
106
107 /*
108 // <o>Region is
109 // <0=>Non-Secure
110 // <1=>Secure, Non-Secure Callable
111 */
112 #define SAU_INIT_NSC1 0
113 /*
114 // </e>
115 */
116
117 /*
118 // <e>Initialize SAU Region 2
119 // <i> Setup SAU Region 2 memory attributes
120 */
121 #define SAU_INIT_REGION2 1
122
123 /*
124 // <o>Start Address <0-0xFFFFFFE0>
125 */
126 #define SAU_INIT_START2 0x20200000
127
128 /*
129 // <o>End Address <0x1F-0xFFFFFFFF>
130 */
131 #define SAU_INIT_END2 0x203FFFFF
132
133 /*
134 // <o>Region is
135 // <0=>Non-Secure
136 // <1=>Secure, Non-Secure Callable
137 */
138 #define SAU_INIT_NSC2 0
139 /*
140 // </e>
141 */
142
143 /*
144 // <e>Initialize SAU Region 3
145 // <i> Setup SAU Region 3 memory attributes
146 */
147 #define SAU_INIT_REGION3 1
148
149 /*
150 // <o>Start Address <0-0xFFFFFFE0>
151 */
152 #define SAU_INIT_START3 0x40000000
153
154 /*
155 // <o>End Address <0x1F-0xFFFFFFFF>
156 */
157 #define SAU_INIT_END3 0x40040000
158
159 /*
160 // <o>Region is
161 // <0=>Non-Secure
162 // <1=>Secure, Non-Secure Callable
163 */
164 #define SAU_INIT_NSC3 0
165 /*
166 // </e>
167 */
168
169 /*
170 // <e>Initialize SAU Region 4
171 // <i> Setup SAU Region 4 memory attributes
172 */
173 #define SAU_INIT_REGION4 0
174
175 /*
176 // <o>Start Address <0-0xFFFFFFE0>
177 */
178 #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
179
180 /*
181 // <o>End Address <0x1F-0xFFFFFFFF>
182 */
183 #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
184
185 /*
186 // <o>Region is
187 // <0=>Non-Secure
188 // <1=>Secure, Non-Secure Callable
189 */
190 #define SAU_INIT_NSC4 0
191 /*
192 // </e>
193 */
194
195 /*
196 // <e>Initialize SAU Region 5
197 // <i> Setup SAU Region 5 memory attributes
198 */
199 #define SAU_INIT_REGION5 0
200
201 /*
202 // <o>Start Address <0-0xFFFFFFE0>
203 */
204 #define SAU_INIT_START5 0x00000000
205
206 /*
207 // <o>End Address <0x1F-0xFFFFFFFF>
208 */
209 #define SAU_INIT_END5 0x00000000
210
211 /*
212 // <o>Region is
213 // <0=>Non-Secure
214 // <1=>Secure, Non-Secure Callable
215 */
216 #define SAU_INIT_NSC5 0
217 /*
218 // </e>
219 */
220
221 /*
222 // <e>Initialize SAU Region 6
223 // <i> Setup SAU Region 6 memory attributes
224 */
225 #define SAU_INIT_REGION6 0
226
227 /*
228 // <o>Start Address <0-0xFFFFFFE0>
229 */
230 #define SAU_INIT_START6 0x00000000
231
232 /*
233 // <o>End Address <0x1F-0xFFFFFFFF>
234 */
235 #define SAU_INIT_END6 0x00000000
236
237 /*
238 // <o>Region is
239 // <0=>Non-Secure
240 // <1=>Secure, Non-Secure Callable
241 */
242 #define SAU_INIT_NSC6 0
243 /*
244 // </e>
245 */
246
247 /*
248 // <e>Initialize SAU Region 7
249 // <i> Setup SAU Region 7 memory attributes
250 */
251 #define SAU_INIT_REGION7 0
252
253 /*
254 // <o>Start Address <0-0xFFFFFFE0>
255 */
256 #define SAU_INIT_START7 0x00000000
257
258 /*
259 // <o>End Address <0x1F-0xFFFFFFFF>
260 */
261 #define SAU_INIT_END7 0x00000000
262
263 /*
264 // <o>Region is
265 // <0=>Non-Secure
266 // <1=>Secure, Non-Secure Callable
267 */
268 #define SAU_INIT_NSC7 0
269 /*
270 // </e>
271 */
272
273 /*
274 // </h>
275 */
276
277 /*
278 // <e>Setup behaviour of Sleep and Exception Handling
279 */
280 #define SCB_CSR_AIRCR_INIT 1
281
282 /*
283 // <o> Deep Sleep can be enabled by
284 // <0=>Secure and Non-Secure state
285 // <1=>Secure state only
286 // <i> Value for SCB->CSR register bit DEEPSLEEPS
287 */
288 #define SCB_CSR_DEEPSLEEPS_VAL 1
289
290 /*
291 // <o>System reset request accessible from
292 // <0=> Secure and Non-Secure state
293 // <1=> Secure state only
294 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
295 */
296 #define SCB_AIRCR_SYSRESETREQS_VAL 1
297
298 /*
299 // <o>Priority of Non-Secure exceptions is
300 // <0=> Not altered
301 // <1=> Lowered to 0x80-0xFF
302 // <i> Value for SCB->AIRCR register bit PRIS
303 */
304 #define SCB_AIRCR_PRIS_VAL 1
305
306 /*
307 // <o>BusFault, HardFault, and NMI target
308 // <0=> Secure state
309 // <1=> Non-Secure state
310 // <i> Value for SCB->AIRCR register bit BFHFNMINS
311 */
312 #define SCB_AIRCR_BFHFNMINS_VAL 0
313
314 /*
315 // </e>
316 */
317
318 /*
319 // <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
320 */
321 #define TZ_FPU_NS_USAGE 1
322
323 /*
324 // <o>Floating Point and Vector Unit usage
325 // <0=> Secure state only
326 // <3=> Secure and Non-Secure state
327 // <i> Value for SCB->NSACR register bits CP10, CP11
328 */
329 #define SCB_NSACR_CP10_11_VAL 3
330
331 /*
332 // <o>Treat floating-point registers as Secure
333 // <0=> Disabled
334 // <1=> Enabled
335 // <i> Value for FPU->FPCCR register bit TS
336 */
337 #define FPU_FPCCR_TS_VAL 0
338
339 /*
340 // <o>Clear on return (CLRONRET) accessibility
341 // <0=> Secure and Non-Secure state
342 // <1=> Secure state only
343 // <i> Value for FPU->FPCCR register bit CLRONRETS
344 */
345 #define FPU_FPCCR_CLRONRETS_VAL 0
346
347 /*
348 // <o>Clear floating-point caller saved registers on exception return
349 // <0=> Disabled
350 // <1=> Enabled
351 // <i> Value for FPU->FPCCR register bit CLRONRET
352 */
353 #define FPU_FPCCR_CLRONRET_VAL 1
354
355 /*
356 // </e>
357 */
358
359 /*
360 // <h>Setup Interrupt Target
361 */
362
363 /*
364 // <e>Initialize ITNS 0 (Interrupts 0..31)
365 */
366 #define NVIC_INIT_ITNS0 1
367
368 /*
369 // Interrupts 0..31
370 // <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
371 // <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
372 // <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
373 // <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
374 // <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
375 // <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
376 // <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
377 // <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
378 // <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
379 // <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
380 // <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
381 // <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
382 // <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
383 // <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
384 // <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
385 // <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
386 // <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
387 // <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
388 // <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
389 // <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
390 // <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
391 // <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
392 // <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
393 // <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
394 // <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
395 // <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
396 // <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
397 // <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
398 // <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
399 // <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
400 // <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
401 // <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
402 */
403 #define NVIC_INIT_ITNS0_VAL 0x00000000
404
405 /*
406 // </e>
407 */
408
409 /*
410 // <e>Initialize ITNS 1 (Interrupts 32..63)
411 */
412 #define NVIC_INIT_ITNS1 1
413
414 /*
415 // Interrupts 32..63
416 // <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
417 // <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
418 // <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
419 // <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
420 // <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
421 // <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
422 // <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
423 // <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
424 // <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
425 // <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
426 // <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
427 // <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
428 // <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
429 // <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
430 // <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
431 // <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
432 // <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
433 // <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
434 // <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
435 // <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
436 // <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
437 // <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
438 // <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
439 // <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
440 // <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
441 // <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
442 // <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
443 // <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
444 // <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
445 // <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
446 // <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
447 // <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
448 */
449 #define NVIC_INIT_ITNS1_VAL 0x00000000
450
451 /*
452 // </e>
453 */
454
455 /*
456 // <e>Initialize ITNS 2 (Interrupts 64..95)
457 */
458 #define NVIC_INIT_ITNS2 0
459
460 /*
461 // Interrupts 64..95
462 // <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
463 // <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
464 // <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
465 // <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
466 // <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
467 // <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
468 // <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
469 // <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
470 // <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
471 // <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
472 // <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
473 // <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
474 // <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
475 // <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
476 // <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
477 // <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
478 // <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
479 // <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
480 // <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
481 // <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
482 // <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
483 // <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
484 // <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
485 // <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
486 // <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
487 // <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
488 // <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
489 // <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
490 // <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
491 // <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
492 // <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
493 // <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
494 */
495 #define NVIC_INIT_ITNS2_VAL 0x00000000
496
497 /*
498 // </e>
499 */
500
501 /*
502 // <e>Initialize ITNS 3 (Interrupts 96..127)
503 */
504 #define NVIC_INIT_ITNS3 0
505
506 /*
507 // Interrupts 96..127
508 // <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
509 // <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
510 // <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
511 // <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
512 // <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
513 // <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
514 // <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
515 // <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
516 // <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
517 // <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
518 // <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
519 // <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
520 // <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
521 // <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
522 // <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
523 // <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
524 // <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
525 // <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
526 // <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
527 // <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
528 // <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
529 // <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
530 // <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
531 // <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
532 // <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
533 // <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
534 // <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
535 // <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
536 // <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
537 // <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
538 // <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
539 // <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
540 */
541 #define NVIC_INIT_ITNS3_VAL 0x00000000
542
543 /*
544 // </e>
545 */
546
547 /*
548 // <e>Initialize ITNS 4 (Interrupts 128..159)
549 */
550 #define NVIC_INIT_ITNS4 0
551
552 /*
553 // Interrupts 128..159
554 // <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
555 // <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
556 // <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
557 // <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
558 // <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
559 // <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
560 // <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
561 // <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
562 // <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
563 // <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
564 // <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
565 // <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
566 // <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
567 // <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
568 // <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
569 // <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
570 // <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
571 // <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
572 // <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
573 // <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
574 // <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
575 // <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
576 // <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
577 // <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
578 // <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
579 // <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
580 // <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
581 // <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
582 // <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
583 // <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
584 // <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
585 // <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
586 */
587 #define NVIC_INIT_ITNS4_VAL 0x00000000
588
589 /*
590 // </e>
591 */
592
593 /*
594 // <e>Initialize ITNS 5 (Interrupts 160..191)
595 */
596 #define NVIC_INIT_ITNS5 0
597
598 /*
599 // Interrupts 160..191
600 // <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
601 // <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
602 // <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
603 // <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
604 // <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
605 // <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
606 // <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
607 // <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
608 // <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
609 // <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
610 // <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
611 // <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
612 // <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
613 // <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
614 // <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
615 // <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
616 // <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
617 // <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
618 // <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
619 // <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
620 // <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
621 // <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
622 // <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
623 // <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
624 // <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
625 // <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
626 // <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
627 // <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
628 // <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
629 // <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
630 // <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
631 // <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
632 */
633 #define NVIC_INIT_ITNS5_VAL 0x00000000
634
635 /*
636 // </e>
637 */
638
639 /*
640 // <e>Initialize ITNS 6 (Interrupts 192..223)
641 */
642 #define NVIC_INIT_ITNS6 0
643
644 /*
645 // Interrupts 192..223
646 // <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
647 // <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
648 // <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
649 // <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
650 // <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
651 // <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
652 // <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
653 // <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
654 // <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
655 // <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
656 // <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
657 // <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
658 // <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
659 // <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
660 // <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
661 // <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
662 // <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
663 // <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
664 // <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
665 // <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
666 // <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
667 // <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
668 // <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
669 // <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
670 // <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
671 // <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
672 // <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
673 // <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
674 // <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
675 // <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
676 // <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
677 // <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
678 */
679 #define NVIC_INIT_ITNS6_VAL 0x00000000
680
681 /*
682 // </e>
683 */
684
685 /*
686 // <e>Initialize ITNS 7 (Interrupts 224..255)
687 */
688 #define NVIC_INIT_ITNS7 0
689
690 /*
691 // Interrupts 224..255
692 // <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
693 // <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
694 // <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
695 // <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
696 // <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
697 // <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
698 // <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
699 // <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
700 // <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
701 // <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
702 // <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
703 // <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
704 // <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
705 // <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
706 // <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
707 // <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
708 // <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
709 // <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
710 // <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
711 // <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
712 // <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
713 // <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
714 // <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
715 // <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
716 // <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
717 // <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
718 // <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
719 // <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
720 // <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
721 // <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
722 // <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
723 // <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
724 */
725 #define NVIC_INIT_ITNS7_VAL 0x00000000
726
727 /*
728 // </e>
729 */
730
731 /*
732 // <e>Initialize ITNS 8 (Interrupts 256..287)
733 */
734 #define NVIC_INIT_ITNS8 0
735
736 /*
737 // Interrupts 256..287
738 // <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
739 // <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
740 // <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
741 // <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
742 // <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
743 // <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
744 // <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
745 // <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
746 // <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
747 // <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
748 // <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
749 // <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
750 // <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
751 // <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
752 // <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
753 // <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
754 // <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
755 // <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
756 // <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
757 // <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
758 // <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
759 // <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
760 // <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
761 // <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
762 // <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
763 // <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
764 // <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
765 // <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
766 // <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
767 // <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
768 // <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
769 // <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
770 */
771 #define NVIC_INIT_ITNS8_VAL 0x00000000
772
773 /*
774 // </e>
775 */
776
777 /*
778 // <e>Initialize ITNS 9 (Interrupts 288..319)
779 */
780 #define NVIC_INIT_ITNS9 0
781
782 /*
783 // Interrupts 288..319
784 // <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
785 // <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
786 // <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
787 // <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
788 // <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
789 // <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
790 // <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
791 // <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
792 // <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
793 // <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
794 // <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
795 // <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
796 // <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
797 // <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
798 // <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
799 // <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
800 // <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
801 // <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
802 // <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
803 // <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
804 // <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
805 // <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
806 // <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
807 // <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
808 // <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
809 // <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
810 // <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
811 // <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
812 // <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
813 // <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
814 // <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
815 // <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
816 */
817 #define NVIC_INIT_ITNS9_VAL 0x00000000
818
819 /*
820 // </e>
821 */
822
823 /*
824 // <e>Initialize ITNS 10 (Interrupts 320..351)
825 */
826 #define NVIC_INIT_ITNS10 0
827
828 /*
829 // Interrupts 320..351
830 // <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
831 // <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
832 // <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
833 // <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
834 // <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
835 // <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
836 // <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
837 // <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
838 // <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
839 // <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
840 // <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
841 // <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
842 // <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
843 // <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
844 // <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
845 // <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
846 // <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
847 // <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
848 // <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
849 // <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
850 // <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
851 // <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
852 // <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
853 // <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
854 // <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
855 // <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
856 // <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
857 // <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
858 // <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
859 // <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
860 // <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
861 // <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
862 */
863 #define NVIC_INIT_ITNS10_VAL 0x00000000
864
865 /*
866 // </e>
867 */
868
869 /*
870 // <e>Initialize ITNS 11 (Interrupts 352..383)
871 */
872 #define NVIC_INIT_ITNS11 0
873
874 /*
875 // Interrupts 352..383
876 // <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
877 // <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
878 // <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
879 // <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
880 // <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
881 // <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
882 // <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
883 // <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
884 // <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
885 // <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
886 // <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
887 // <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
888 // <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
889 // <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
890 // <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
891 // <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
892 // <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
893 // <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
894 // <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
895 // <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
896 // <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
897 // <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
898 // <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
899 // <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
900 // <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
901 // <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
902 // <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
903 // <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
904 // <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
905 // <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
906 // <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
907 // <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
908 */
909 #define NVIC_INIT_ITNS11_VAL 0x00000000
910
911 /*
912 // </e>
913 */
914
915 /*
916 // <e>Initialize ITNS 12 (Interrupts 384..415)
917 */
918 #define NVIC_INIT_ITNS12 0
919
920 /*
921 // Interrupts 384..415
922 // <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
923 // <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
924 // <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
925 // <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
926 // <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
927 // <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
928 // <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
929 // <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
930 // <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
931 // <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
932 // <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
933 // <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
934 // <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
935 // <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
936 // <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
937 // <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
938 // <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
939 // <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
940 // <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
941 // <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
942 // <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
943 // <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
944 // <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
945 // <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
946 // <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
947 // <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
948 // <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
949 // <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
950 // <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
951 // <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
952 // <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
953 // <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
954 */
955 #define NVIC_INIT_ITNS12_VAL 0x00000000
956
957 /*
958 // </e>
959 */
960
961 /*
962 // <e>Initialize ITNS 13 (Interrupts 416..447)
963 */
964 #define NVIC_INIT_ITNS13 0
965
966 /*
967 // Interrupts 416..447
968 // <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
969 // <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
970 // <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
971 // <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
972 // <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
973 // <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
974 // <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
975 // <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
976 // <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
977 // <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
978 // <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
979 // <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
980 // <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
981 // <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
982 // <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
983 // <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
984 // <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
985 // <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
986 // <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
987 // <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
988 // <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
989 // <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
990 // <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
991 // <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
992 // <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
993 // <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
994 // <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
995 // <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
996 // <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
997 // <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
998 // <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
999 // <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
1000 */
1001 #define NVIC_INIT_ITNS13_VAL 0x00000000
1002
1003 /*
1004 // </e>
1005 */
1006
1007 /*
1008 // <e>Initialize ITNS 14 (Interrupts 448..479)
1009 */
1010 #define NVIC_INIT_ITNS14 0
1011
1012 /*
1013 // Interrupts 448..479
1014 // <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
1015 // <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
1016 // <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
1017 // <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
1018 // <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
1019 // <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
1020 // <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
1021 // <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
1022 // <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
1023 // <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
1024 // <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
1025 // <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
1026 // <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
1027 // <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
1028 // <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
1029 // <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
1030 // <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
1031 // <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
1032 // <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
1033 // <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
1034 // <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
1035 // <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
1036 // <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
1037 // <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
1038 // <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
1039 // <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
1040 // <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
1041 // <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
1042 // <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
1043 // <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
1044 // <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
1045 // <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
1046 */
1047 #define NVIC_INIT_ITNS14_VAL 0x00000000
1048
1049 /*
1050 // </e>
1051 */
1052
1053 /*
1054 // <e>Initialize ITNS 15 (Interrupts 480..511)
1055 */
1056 #define NVIC_INIT_ITNS15 0
1057
1058 /*
1059 // Interrupts 480..511
1060 // <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
1061 // <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
1062 // <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
1063 // <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
1064 // <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
1065 // <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
1066 // <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
1067 // <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
1068 // <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
1069 // <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
1070 // <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
1071 // <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
1072 // <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
1073 // <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
1074 // <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
1075 // <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
1076 // <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
1077 // <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
1078 // <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
1079 // <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
1080 // <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
1081 // <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
1082 // <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
1083 // <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
1084 // <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
1085 // <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
1086 // <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
1087 // <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
1088 // <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
1089 // <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
1090 // <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
1091 // <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
1092 */
1093 #define NVIC_INIT_ITNS15_VAL 0x00000000
1094
1095 /*
1096 // </e>
1097 */
1098
1099 /*
1100 // </h>
1101 */
1102
1103
1104
1105 /*
1106 max 128 SAU regions.
1107 SAU regions are defined in partition.h
1108 */
1109
1110 #define SAU_INIT_REGION(n) \
1111 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1112 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1113 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1114 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
1115
1116 /**
1117 \brief Setup a SAU Region
1118 \details Writes the region information contained in SAU_Region to the
1119 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
1120 */
TZ_SAU_Setup(void)1121 __STATIC_INLINE void TZ_SAU_Setup (void)
1122 {
1123
1124 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1125
1126 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
1127 SAU_INIT_REGION(0);
1128 #endif
1129
1130 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
1131 SAU_INIT_REGION(1);
1132 #endif
1133
1134 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
1135 SAU_INIT_REGION(2);
1136 #endif
1137
1138 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
1139 SAU_INIT_REGION(3);
1140 #endif
1141
1142 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
1143 SAU_INIT_REGION(4);
1144 #endif
1145
1146 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
1147 SAU_INIT_REGION(5);
1148 #endif
1149
1150 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
1151 SAU_INIT_REGION(6);
1152 #endif
1153
1154 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
1155 SAU_INIT_REGION(7);
1156 #endif
1157
1158 /* repeat this for all possible SAU regions */
1159
1160 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1161
1162
1163 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
1164 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
1165 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
1166 #endif
1167
1168 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
1169 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
1170 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
1171
1172 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
1173 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
1174 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
1175 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
1176 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
1177 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
1178 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
1179
1180 #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
1181 (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
1182 (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
1183
1184 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
1185 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
1186
1187 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
1188 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
1189 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
1190 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
1191 #endif
1192
1193 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
1194 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
1195 #endif
1196
1197 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
1198 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
1199 #endif
1200
1201 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
1202 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
1203 #endif
1204
1205 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
1206 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
1207 #endif
1208
1209 #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
1210 NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
1211 #endif
1212
1213 #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
1214 NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
1215 #endif
1216
1217 #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
1218 NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
1219 #endif
1220
1221 #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
1222 NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
1223 #endif
1224
1225 #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
1226 NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
1227 #endif
1228
1229 #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
1230 NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
1231 #endif
1232
1233 #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
1234 NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
1235 #endif
1236
1237 #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
1238 NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
1239 #endif
1240
1241 #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
1242 NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
1243 #endif
1244
1245 #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
1246 NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
1247 #endif
1248
1249 #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
1250 NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
1251 #endif
1252
1253 #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
1254 NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
1255 #endif
1256
1257 /* repeat this for all possible ITNS elements */
1258
1259 }
1260
1261 #endif /* PARTITION_ARMCM55_H */
1262