/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
D | IntrinsicsAMDGPU.td | 183 // Set EXEC according to a thread count packed in an SGPR input: 187 [llvm_i32_ty, // 32-bit SGPR input 695 [llvm_v8i32_ty], // rsrc(SGPR) 696 !if(P_.IsSample, [llvm_v4i32_ty, // samp(SGPR) 859 [llvm_v4i32_ty, // rsrc(SGPR) 861 llvm_i32_ty, // offset(SGPR/VGPR/imm) 871 [llvm_v4i32_ty, // rsrc(SGPR) 872 llvm_i32_ty, // byte offset(SGPR/imm) 880 llvm_v4i32_ty, // rsrc(SGPR) 882 llvm_i32_ty, // offset(SGPR/VGPR/imm) [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.td | 194 // SGPR registers 196 def SGPR#Index : SIReg <"s"#Index, Index>; 229 // SGPR 32-bit registers 231 (add (sequence "SGPR%u", 0, 105))> { 232 // Give all SGPR classes higher priority than VGPR classes, because 237 // SGPR 64-bit registers 240 // SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 243 // SGPR 128-bit registers 246 // SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 249 // SGPR 256-bit registers [all …]
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D | AMDGPURegisterBanks.td | 9 def SGPRRegBank : RegisterBank<"SGPR",
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D | AMDGPUGenRegisterBankInfo.def | 48 {0, 1, SGPRRegBank}, // SGPR begin 262 // the register bank is SGPR or if we don't know how to handle the vector
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D | AMDGPUCallingConv.td | 93 (sequence "SGPR%u", 32, 105) 103 (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
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D | AMDGPU.td | 148 "VI SGPR initialization bug requiring a fixed SGPR allocation size" 172 …"VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution… 460 "V_CMPX does not write VCC/SGPR in addition to EXEC"
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D | SIInstrInfo.cpp | 3463 if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) { in verifyInstruction() argument 3464 return !RI.regsOverlap(SGPRUsed, SGPR); in verifyInstruction() 3985 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg()); in isOperandLegal() local 3986 if (!SGPRsUsed.count(SGPR) && in isOperandLegal() 3990 SGPRsUsed.insert(SGPR); in isOperandLegal() 4245 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in readlaneVGPRToSGPR() local 4247 get(AMDGPU::V_READFIRSTLANE_B32), SGPR) in readlaneVGPRToSGPR() 4249 SRegs.push_back(SGPR); in readlaneVGPRToSGPR() 4271 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD() local 4272 SBase->setReg(SGPR); in legalizeOperandsSMRD() [all …]
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D | SIInstructions.td | 496 // TODO: We can support indirect SGPR access. 1007 // FIXME: Make SGPR 1221 // TODO: Use SGPR for constant 1232 // TODO: Use SGPR for constant 1538 // comparisons may write to a pair of SGPRs or a single SGPR, so treat 1539 // these as 32 or 64-bit comparisons. When legalizing SGPR copies,
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D | SIInstrInfo.td | 84 SDTCisVT<4, i32>, // soffset(SGPR) 102 SDTCisVT<4, i32>, // soffset(SGPR) 120 SDTCisVT<4, i32>, // soffset(SGPR) 146 SDTCisVT<4, i32>, // soffset(SGPR) 171 SDTCisVT<5, i32>, // soffset(SGPR) 184 SDTCisVT<4, i32>, // soffset(SGPR) 214 SDTCisVT<6, i32>, // soffset(SGPR)
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D | VOPInstructions.td | 422 // than VGPRs (at most 1 can be an SGPR); 425 // replaces OMOD and the dest fields with SD and SDST (SGPR destination)
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D | VOP2Instructions.td | 342 // Write out to vcc or arbitrary SGPR. 355 // Write out to vcc or arbitrary SGPR and read in from vcc or 356 // arbitrary SGPR. 391 // Read in from vcc or arbitrary SGPR.
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D | AMDGPURegisterBankInfo.cpp | 1081 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in constrainOpWithReadfirstlane() local 1083 .addDef(SGPR) in constrainOpWithReadfirstlane() 1086 MRI.setType(SGPR, MRI.getType(Reg)); in constrainOpWithReadfirstlane() 1093 MI.getOperand(OpIdx).setReg(SGPR); in constrainOpWithReadfirstlane()
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D | SMInstructions.td | 755 // 3. SGPR offset 783 // 3. Offset loaded in an 32bit SGPR
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D | VOP3Instructions.td | 554 // is in an SGPR (uniform values can end up in VGPRs as well).
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/third_party/mesa3d/src/amd/compiler/ |
D | README-ISA.md | 191 ## SGPR offset on MUBUF prevents addr clamping on SI/CI 219 VMEM/FLAT/GLOBAL/SCRATCH/DS instruction reads an SGPR (or EXEC, or M0). 220 Then, a SALU/SMEM instruction writes the same SGPR. 228 An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR. 271 A VALU instruction that writes an SGPR (or has a valid SDST operand), or `s_waitcnt_depctr 0xfffe`.
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/third_party/vk-gl-cts/external/vulkan-docs/src/appendices/ |
D | VK_AMD_shader_info.txt | 58 printf("SGPR usage: %d\n", statistics.resourceUsage.numUsedSgprs);
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/third_party/mesa3d/docs/relnotes/ |
D | 21.3.1.rst | 113 - aco: don't create DPP instructions with SGPR operands
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D | 21.1.3.rst | 134 - aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7
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D | 18.1.9.rst | 61 - radv: Set the user SGPR MSB for Vega.
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D | 21.1.2.rst | 165 - aco: fix derivatives/intrinsics with SGPR sources
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D | 17.1.2.rst | 49 - radv: Reserve space for descriptor and push constant user SGPR
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D | 18.2.1.rst | 74 - radv: Set the user SGPR MSB for Vega.
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D | 19.3.4.rst | 171 - aco: fix operand to scc when selecting SGPR ufind_msb/ifind_msb
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D | 21.0.0.rst | 2051 - radeonsi: swap DrawId and StartInstance SGPR locations 2163 - radeonsi: don't update indexed flag in SGPR if it's unused 2164 - radeonsi: don't update provoking vertex and outprim states in SGPR if unused 2802 - aco: try to better align 8+ dword SGPR vectors
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D | 22.2.0.rst | 1403 - aco/optimizer: prevent any overflow between SGPR and const offset on MUBUF 3921 - radeonsi/gfx11: use the new TCS WaveID SGPR to compute vs_rel_patch_id 3938 - radeonsi/gfx11: don't count the non-existent scratch_byte_offset SGPR 4111 - radeonsi: move the no-AA small prim precision cull constant into an SGPR 5167 - aco: fix disassembly of SMEM with both SGPR and constant offset 5414 - radv,aco: use the new TCS WaveID SGPR to compute vs_rel_patch_id on GFX11 5562 - radv: declare a new user SGPR arg in FS for the epilog PC
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