Searched refs:SGPR0 (Results 1 – 9 of 9) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUCallingConv.td | 22 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, 54 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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D | SIInsertWaitcnts.cpp | 126 unsigned SGPR0; member 487 assert(Reg >= RegisterEncoding.SGPR0 && Reg < SQ_MAX_PGM_SGPRS); in getRegInterval() 488 Result.first = Reg - RegisterEncoding.SGPR0 + NUM_ALL_VGPRS; in getRegInterval() 1490 RegisterEncoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0); in runOnMachineFunction() 1492 RegisterEncoding.SGPR0 + HardwareLimits.NumSGPRsMax - 1; in runOnMachineFunction()
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D | SIMachineFunctionInfo.cpp | 410 return AMDGPU::SGPR0 + NumUserSGPRs; in getNextUserSGPR() 414 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; in getNextSystemSGPR()
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D | GCNRegBankReassign.cpp | 596 : AMDGPU::SGPR0); in scavengeReg()
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D | SIFrameLowering.cpp | 560 auto GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in in emitEntryFunctionScratchSetup()
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D | SIRegisterInfo.cpp | 72 classifyPressureSet(i, AMDGPU::SGPR0, SGPRPressureSets); in SIRegisterInfo()
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D | SOPInstructions.td | 725 // SCC = S_CMPK_EQ_I32 SGPR0, imm
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D | SIISelLowering.cpp | 111 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) { in findFirstFreeSGPR() 112 return AMDGPU::SGPR0 + Reg; in findFirstFreeSGPR()
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/third_party/mesa3d/docs/relnotes/ |
D | 22.2.0.rst | 855 - radv: update the initialization of SGPR0/1 registers for HS and GS on GFX11 3936 - radeonsi/gfx11: update the initialization of SGPR0/1 registers for HS and GS
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