Searched refs:SOP1 (Results 1 – 13 of 13) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 54 SOP1 = 1 variable in Format
426 SOP1 = { variable
499 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
500 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
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| D | aco_ir.h | 71 SOP1 = 1, enumerator
1060 constexpr bool isSOP1() const noexcept { return format == Format::SOP1; } in isSOP1()
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| D | aco_insert_NOPs.cpp | 759 create_instruction<SOP1_instruction>(aco_opcode::s_mov_b32, Format::SOP1, 1, 1)}; in handle_instruction_gfx10()
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| D | aco_assembler.cpp | 150 case Format::SOP1: { in emit_instruction()
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| D | aco_insert_exec_mask.cpp | 611 Format::SOP1, 1, 1)); in process_instructions()
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| D | aco_spill.cpp | 290 if (instr->format != Format::VOP1 && instr->format != Format::SOP1 && in should_rematerialize()
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| D | aco_register_allocation.cpp | 3054 Format::SOP1, 1, 1)); in register_allocation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 21 field bit SOP1 = 0;
134 let TSFlags{2} = SOP1;
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| D | SIDefines.h | 25 SOP1 = 1 << 2, enumerator
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| D | SOPInstructions.td | 37 // SOP1 Instructions
48 let SOP1 = 1;
1199 // SOP1 Patterns
1269 // SOP1 - GFX10.
1302 // SOP1 - GFX6, GFX7.
1660 // SOP1 - GFX9.
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| D | SIInstrInfo.h | 358 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
362 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 22.1.3.rst | 185 - aco: fix validation of SOP1 instructions without definitions
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| D | 22.2.0.rst | 5536 - aco: fix validation of SOP1 instructions without definitions
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