Searched refs:SOPC (Results 1 – 10 of 10) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 58 SOPC = 5 variable in Format
504 SOPC = { variable
527 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
528 opcode(name, gfx7, gfx9, gfx10, Format.SOPC, InstrClass.Salu)
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| D | aco_optimizer.cpp | 4632 #define SOPC(op) \ in sopc_is_signed() macro
4636 SOPC(eq) in sopc_is_signed()
4637 SOPC(lg) in sopc_is_signed()
4638 SOPC(gt) in sopc_is_signed()
4639 SOPC(ge) in sopc_is_signed()
4640 SOPC(lt) in sopc_is_signed()
4641 SOPC(le) in sopc_is_signed()
4644 #undef SOPC in sopc_is_signed()
4650 #define SOPC(op1, op2) \ in sopc_32_swapped() macro
4654 SOPC(eq, eq) in sopc_32_swapped()
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| D | aco_ir.h | 75 SOPC = 5, enumerator
1104 constexpr bool isSOPC() const noexcept { return format == Format::SOPC; } in isSOPC()
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| D | aco_assembler.cpp | 158 case Format::SOPC: { in emit_instruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 23 field bit SOPC = 0;
136 let TSFlags{4} = SOPC;
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| D | SIDefines.h | 27 SOPC = 1 << 4, enumerator
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| D | SOPInstructions.td | 835 // SOPC Instructions
848 class SOPC <bits<7> op, dag outs, dag ins, string asm,
855 let SOPC = 1;
863 string opName, list<dag> pattern = []> : SOPC <
923 def S_SET_GPR_IDX_ON : SOPC <0x11,
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| D | SIInstrInfo.h | 374 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
378 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3341 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 22.2.0.rst | 2283 - aco/ir: Pad SOP2 and SOPC to the same size as SOPK.
2286 - aco/optimizer: Optimize SOPC with literal to SOPK.
2288 - aco: Fix swapping sources in SOPC -> SOPK optimization.
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