Searched refs:SRsrc (Results 1 – 2 of 2) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelDAGToDAG.cpp | 208 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, 212 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, 216 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, 223 SDValue Addr, SDValue &SRsrc, SDValue &Soffset, 226 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset, 229 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, 231 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, 1433 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument 1455 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64() 1462 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument [all …]
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D | SIInstrInfo.cpp | 4356 Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass); in emitLoadSRsrcFromVGPRLoop() local 4368 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc) in emitLoadSRsrcFromVGPRLoop() 4379 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop() 4384 .addReg(SRsrc, 0, AMDGPU::sub0_sub1) in emitLoadSRsrcFromVGPRLoop() 4387 .addReg(SRsrc, 0, AMDGPU::sub2_sub3) in emitLoadSRsrcFromVGPRLoop() 4660 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local 4661 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { in legalizeOperands() 4662 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); in legalizeOperands() 4663 SRsrc->setReg(SGPR); in legalizeOperands()
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