Searched refs:SRsrcSub0 (Results 1 – 1 of 1) sorted by relevance
4352 Register SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in emitLoadSRsrcFromVGPRLoop() local4359 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0) in emitLoadSRsrcFromVGPRLoop()4369 .addReg(SRsrcSub0) in emitLoadSRsrcFromVGPRLoop()