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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp4352 Register SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in emitLoadSRsrcFromVGPRLoop() local
4359 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0) in emitLoadSRsrcFromVGPRLoop()
4369 .addReg(SRsrcSub0) in emitLoadSRsrcFromVGPRLoop()