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Searched refs:SSE4_1 (Results 1 – 24 of 24) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/src/Common/
DCPUID.hpp60 static bool SSE4_1; member in sw::CPUID
123 return SSE4_1 && enableSSE4_1; in supportsSSE4_1()
DCPUID.cpp38 bool CPUID::SSE4_1 = detectSSE4_1(); member in sw::CPUID
227 return SSE4_1 = (registers[2] & 0x00080000) != 0; in detectSSE4_1()
/third_party/node/deps/v8/src/wasm/baseline/x64/
Dliftoff-assembler-x64.h1639 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_ceil()
1645 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_floor()
1651 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_trunc()
1658 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_nearest_int()
1772 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_ceil()
1778 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_floor()
1784 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_trunc()
1791 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_nearest_int()
1842 if (!CpuFeatures::IsSupported(SSE4_1)) { in EmitTruncateFloatToInt()
1846 CpuFeatureScope feature(assm, SSE4_1); in EmitTruncateFloatToInt()
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/third_party/node/deps/v8/src/codegen/shared-ia32-x64/
Dmacro-assembler-shared-ia32-x64.cc112 CpuFeatureScope scope(this, SSE4_1); in Pblendvb()
162 CpuFeatureScope scope(this, SSE4_1); in F64x2ReplaceLane()
650 CpuFeatureScope sse_scope(this, SSE4_1); in I16x8SConvertI8x16High()
676 CpuFeatureScope sse_scope(this, SSE4_1); in I16x8UConvertI8x16High()
720 } else if (CpuFeatures::IsSupported(SSE4_1)) { in I32x4ExtAddPairwiseI16x8U()
721 CpuFeatureScope sse_scope(this, SSE4_1); in I32x4ExtAddPairwiseI16x8U()
779 CpuFeatureScope sse_scope(this, SSE4_1); in I32x4SConvertI16x8High()
810 CpuFeatureScope sse_scope(this, SSE4_1); in I32x4UConvertI16x8High()
1061 CpuFeatureScope sse4_scope(this, SSE4_1); in I64x2ExtMul()
1077 CpuFeatureScope sse_scope(this, SSE4_1); in I64x2SConvertI32x4High()
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Dmacro-assembler-shared-ia32-x64.h60 imm8, load_pc_offset, {SSE4_1});
207 AvxHelper<Dst, Arg, Args...>{this, base::Optional<CpuFeature>(SSE4_1)} \
572 } else if (CpuFeatures::IsSupported(SSE4_1)) { in Pextrd()
573 CpuFeatureScope sse_scope(this, SSE4_1); in Pextrd()
584 if (CpuFeatures::IsSupported(SSE4_1)) {
587 base::Optional<CpuFeature>(SSE4_1));
724 CpuFeatureScope scope(this, SSE4_1); in I32x4TruncSatF64x2UZero()
/third_party/node/deps/v8/src/wasm/baseline/ia32/
Dliftoff-assembler-ia32.h2042 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_ceil()
2048 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_floor()
2054 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_trunc()
2061 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f32_nearest_int()
2179 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_ceil()
2185 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_floor()
2191 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_trunc()
2198 RETURN_FALSE_IF_MISSING_CPU_FEATURE(SSE4_1); in emit_f64_nearest_int()
2240 if (!CpuFeatures::IsSupported(SSE4_1)) { in EmitTruncateFloatToInt()
2244 CpuFeatureScope feature(assm, SSE4_1); in EmitTruncateFloatToInt()
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/third_party/node/deps/v8/src/codegen/ia32/
Dassembler-ia32.cc127 if (IsSupported(SSE4_1)) return true; in SupportsWasmSimd128()
142 if (cpu.has_sse41()) SetSupported(SSE4_1); in ProbeImpl()
167 if (!FLAG_enable_sse4_1 || !IsSupported(SSSE3)) SetUnsupported(SSE4_1); in ProbeImpl()
168 if (!FLAG_enable_sse4_2 || !IsSupported(SSE4_1)) SetUnsupported(SSE4_2); in ProbeImpl()
187 CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(AVX), in PrintFeatures()
328 EnableCpuFeature(SSE4_1); in Assembler()
330 if (CpuFeatures::IsSupported(SSE4_1)) { in Assembler()
2267 DCHECK(IsEnabled(SSE4_1)); in roundps()
2279 DCHECK(IsEnabled(SSE4_1)); in roundpd()
2291 DCHECK(IsEnabled(SSE4_1)); in roundss()
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Dmacro-assembler-ia32.cc1581 } else if (CpuFeatures::IsSupported(SSE4_1)) { in CallRecordWriteStub()
1582 CpuFeatureScope scope(this, SSE4_1); in CallRecordWriteStub()
/third_party/node/deps/v8/src/codegen/
Dcpu-features.h18 SSE4_1, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTargetLoweringX86.h31 SSE4_1, enumerator
DIceInstX8664.h1897 Dest->getType() == IceType_v8i16 || getInstructionSet(Func) >= SSE4_1; in create()
2106 getInstructionSet(Func) >= SSE4_1);
2124 assert(Dest->getType() != IceType_f64 || getInstructionSet(Func) >= SSE4_1); in create()
2214 getInstructionSet(Func) >= SSE4_1); in create()
2246 assert(getInstructionSet(Func) >= SSE4_1); in create()
2264 assert(getInstructionSet(Func) >= SSE4_1); in create()
2284 getInstructionSet(Func) >= SSE4_1); in create()
DIceInstX8632.h1956 Dest->getType() == IceType_v8i16 || getInstructionSet(Func) >= SSE4_1; in create()
2165 getInstructionSet(Func) >= SSE4_1);
2183 assert(Dest->getType() != IceType_f64 || getInstructionSet(Func) >= SSE4_1); in create()
2273 getInstructionSet(Func) >= SSE4_1); in create()
2305 assert(getInstructionSet(Func) >= SSE4_1); in create()
2323 assert(getInstructionSet(Func) >= SSE4_1); in create()
2343 getInstructionSet(Func) >= SSE4_1); in create()
DIceTargetLoweringX8664.cpp1724 Ty == IceType_v8i16 || InstructionSet >= SSE4_1; in lowerArithmetic()
2706 (InstructionSet >= SSE4_1 && Ty != IceType_v4f32); in lowerExtractElement()
3215 if (Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1) { in lowerInsertElement()
3811 assert(InstructionSet >= SSE4_1); in lowerIntrinsic()
5296 if (InstructionSet < SSE4_1) { in lowerShuffleVector()
5368 if (InstructionSet < SSE4_1) { in lowerShuffleVector()
5775 if (InstructionSet >= SSE4_1) { in lowerSelectVector()
DIceTargetLoweringX8632.cpp1924 Ty == IceType_v8i16 || InstructionSet >= SSE4_1; in lowerArithmetic()
3003 (InstructionSet >= SSE4_1 && Ty != IceType_v4f32); in lowerExtractElement()
3659 if (Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1) { in lowerInsertElement()
4278 assert(InstructionSet >= SSE4_1); in lowerIntrinsic()
5886 if (InstructionSet < SSE4_1) { in lowerShuffleVector()
5958 if (InstructionSet < SSE4_1) { in lowerShuffleVector()
6388 if (InstructionSet >= SSE4_1) { in lowerSelectVector()
DIceInstX8664.cpp1155 assert(getInstructionSet(Func) >= SSE4_1); in emitIAS()
1655 assert(getInstructionSet(Func) >= SSE4_1); in emitIAS()
DIceInstX8632.cpp1163 assert(InstX86Base::getTarget(Func)->getInstructionSet() >= SSE4_1); in emitIAS()
1653 assert(InstX86Base::getTarget(Func)->getInstructionSet() >= SSE4_1); in emitIAS()
/third_party/node/deps/v8/src/codegen/x64/
Dassembler-x64.cc80 if (IsSupported(SSE4_1)) return true; in SupportsWasmSimd128()
96 if (cpu.has_sse41()) SetSupported(SSE4_1); in ProbeImpl()
123 if (!FLAG_enable_sse4_1 || !IsSupported(SSSE3)) SetUnsupported(SSE4_1); in ProbeImpl()
124 if (!FLAG_enable_sse4_2 || !IsSupported(SSE4_1)) SetUnsupported(SSE4_2); in ProbeImpl()
150 CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(SSE4_2), in PrintFeatures()
357 EnableCpuFeature(SSE4_1); in Assembler()
359 if (CpuFeatures::IsSupported(SSE4_1)) { in Assembler()
2864 DCHECK(IsEnabled(SSE4_1)); in pextrq()
2876 DCHECK(IsEnabled(SSE4_1)); in pinsrq()
2888 DCHECK(IsEnabled(SSE4_1)); in pinsrq()
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Dmacro-assembler-x64.cc897 CpuFeatureScope sse_scope(this, SSE4_1); in CallRecordWriteStub()
2107 imm8, load_pc_offset, {SSE4_1}); in CallRecordWriteStub()
2113 imm8, load_pc_offset, {SSE4_1}); in CallRecordWriteStub()
/third_party/node/deps/v8/src/compiler/backend/ia32/
Dcode-generator-ia32.cc1277 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2114 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2325 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2333 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2411 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2433 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2626 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2648 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2697 ASSEMBLE_SIMD_PINSR(pinsrb, SSE4_1); in AssembleArchInstruction()
2701 ASSEMBLE_SIMD_PINSR(pinsrw, SSE4_1); in AssembleArchInstruction()
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Dinstruction-selector-ia32.cc3316 if (CpuFeatures::IsSupported(SSE4_1)) { in SupportedMachineOperatorFlags()
/third_party/mesa3d/docs/relnotes/
D10.5.4.rst72 - android: mesa: fix the path of the SSE4_1 optimisations
/third_party/skia/third_party/externals/swiftshader/src/Reactor/
DSubzeroReactor.cpp291 const static bool SSE4_1; member in __anon57b1dc4c0411::CPUID
338 const bool CPUID::SSE4_1 = CPUID::detectSSE4_1(); member in __anon57b1dc4c0411::CPUID
895 …Flags.setTargetInstructionSet(CPUID::SSE4_1 ? Ice::X86InstructionSet_SSE4_1 : Ice::X86InstructionS… in Nucleus()
2812 if(CPUID::SSE4_1) in UShort4()
3664 if(emulateIntrinsics || !(CPUID::SSE4_1 || CPUID::ARM)) in PackUnsigned()
4134 else if(CPUID::SSE4_1) in Round()
4154 if(CPUID::SSE4_1) in Trunc()
4176 if(CPUID::SSE4_1) in Frac()
4195 if(CPUID::SSE4_1) in Floor()
4215 if(CPUID::SSE4_1) in Ceil()
/third_party/node/deps/v8/src/compiler/backend/x64/
Dcode-generator-x64.cc1794 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
1987 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
2026 if (CpuFeatures::IsSupported(SSE4_1) || CpuFeatures::IsSupported(AVX)) { in AssembleArchInstruction()
2086 if (CpuFeatures::IsSupported(SSE4_1) || CpuFeatures::IsSupported(AVX)) { in AssembleArchInstruction()
3077 CpuFeatureScope sse_scope(tasm(), SSE4_1); in AssembleArchInstruction()
Dinstruction-selector-x64.cc4075 if (CpuFeatures::IsSupported(SSE4_1)) { in SupportedMachineOperatorFlags()