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/third_party/libffi/m4/
Dax_enable_builddir.m490 AS_VAR_PUSHDEF([SUB],[ax_enable_builddir])dnl
93 SUB="."
96 ,[SUB="$enableval"], [SUB="auto"])
102 test ".$SUB" = "." && SUB="."
103 test ".$SUB" = ".no" && SUB="."
105 test ".$SUB" = ".auto" && SUB="m4_ifval([$1], [$1],[$TARGET])"
106 if test ".$SUB" != ".." ; then # we know where to go and
107 AS_MKDIR_P([$SUB])
108 echo __.$SUB.__ > $SUB/conftest.tmp
109 cd $SUB
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiAluCode.h25 SUB = 0x02, enumerator
82 case SUB: in lanaiAluCodeToString()
107 .Case("sub", SUB) in stringToLanaiAluCode()
124 case ISD::SUB: in isdToLanaiAluCode()
125 return AluCode::SUB; in isdToLanaiAluCode()
/third_party/mbedtls/library/
Decdsa.c165 #define ECDSA_RS_ENTER(SUB) do { \ argument
172 rs_ctx != NULL && rs_ctx->SUB == NULL) \
174 rs_ctx->SUB = mbedtls_calloc(1, sizeof(*rs_ctx->SUB)); \
175 if (rs_ctx->SUB == NULL) \
178 ecdsa_restart_## SUB ##_init(rs_ctx->SUB); \
183 #define ECDSA_RS_LEAVE(SUB) do { \ argument
185 if (rs_ctx != NULL && rs_ctx->SUB != NULL && \
188 ecdsa_restart_## SUB ##_free(rs_ctx->SUB); \
189 mbedtls_free(rs_ctx->SUB); \
190 rs_ctx->SUB = NULL; \
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Decp_curves.c5015 #define SUB(j) cur -= A(j) macro
5074 SUB(7); SUB(11); NEXT; // A0 += -A7 - A11 in mbedtls_ecp_mod_p224_raw()
5075 SUB(8); SUB(12); NEXT; // A1 += -A8 - A12 in mbedtls_ecp_mod_p224_raw()
5076 SUB(9); SUB(13); NEXT; // A2 += -A9 - A13 in mbedtls_ecp_mod_p224_raw()
5077 SUB(10); ADD(7); ADD(11); NEXT; // A3 += -A10 + A7 + A11 in mbedtls_ecp_mod_p224_raw()
5078 SUB(11); ADD(8); ADD(12); NEXT; // A4 += -A11 + A8 + A12 in mbedtls_ecp_mod_p224_raw()
5079 SUB(12); ADD(9); ADD(13); NEXT; // A5 += -A12 + A9 + A13 in mbedtls_ecp_mod_p224_raw()
5080 SUB(13); ADD(10); // A6 += -A13 + A10 in mbedtls_ecp_mod_p224_raw()
5128 SUB(11); SUB(12); SUB(13); SUB(14); NEXT; // A0 in mbedtls_ecp_mod_p256_raw()
5131 SUB(12); SUB(13); SUB(14); SUB(15); NEXT; // A1 in mbedtls_ecp_mod_p256_raw()
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/third_party/skia/third_party/externals/harfbuzz/src/
Dhb-ot-shape-complex-use-table.hh63 #define SUB USE(SUB) /* CONS_SUB */ macro
266 …, VMAbv, VMAbv, VBlw, O, VMAbv, VMAbv, B, B, B, B, B, SUB, SUB, SUB,
267 …/* 0F90 */ SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, O, SUB, SUB, SUB, S…
268 …/* 0FA0 */ SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, S…
269 …/* 0FB0 */ SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, S…
343 …/* 1920 */ VAbv, VAbv, VBlw, VPst, VPst, VAbv, VAbv, VAbv, VAbv, SUB, SUB, SUB, …
374 … B, B, B, B, B, MPre, MBlw, SUB, FAbv, FAbv, MAbv, SUB, SUB, SUB, …
398 …/* 1BA0 */ B, SUB, SUB, SUB, VAbv, VBlw, VPre, VPst, VAbv, VAbv, VPst, H, S…
412 …/* 1C20 */ B, B, B, B, SUB, SUB, VPst, VPre, VPre, VPre, VPst, VPst, VB…
878 …/* 11C90 */ O, O, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, SUB, …
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/third_party/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json42 "Sub", // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
43 // SUB<c>{<q>} <Rdn>, #<imm8> ; T2
44 // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
154 "Sub" // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
192 "Sub" // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
Dcond-rd-rn-operand-imm12-t32.json37 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
38 // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
96 "Sub" // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
97 // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
Dcond-rd-rn-operand-const-a32.json50 "Sub", // SUB{<c>}{<q>} <Rd>, PC, #<const> ; A2
51 // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
52 // SUB{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
Dcond-rd-rn-operand-rm-t32.json101 "Sub", // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
102 // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
103 // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
104 // SUB{<c>} {<Rd>}, SP, <Rm> ; T1
210 "Sub" // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
/third_party/node/deps/openssl/openssl/crypto/bn/asm/
Dbn-c64xplus.asm173 [A2] SUB A1:A0,1,A1:A0
200 [!A1] SUB A3,A6,A3 ; hi-=dv
209 [!A1] SUB A3,A6,A3 ; hi-=dv
236 || SUB B0,2,B1 ; N-2, initial ILC
237 || SUB B0,1,B2 ; const B2=N-1
247 || SUB A0,1,A0
272 || [A0] SUB.L A0,1,A0
/third_party/openssl/crypto/bn/asm/
Dbn-c64xplus.asm173 [A2] SUB A1:A0,1,A1:A0
200 [!A1] SUB A3,A6,A3 ; hi-=dv
209 [!A1] SUB A3,A6,A3 ; hi-=dv
236 || SUB B0,2,B1 ; N-2, initial ILC
237 || SUB B0,1,B2 ; const B2=N-1
247 || SUB A0,1,A0
272 || [A0] SUB.L A0,1,A0
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td172 (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
174 (AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
176 (AMOADD_W_RL GPR:$addr, (SUB X0, GPR:$incr))>;
178 (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
180 (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
339 (AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
341 (AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
343 (AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
345 (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
347 (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
/third_party/skia/third_party/externals/opengl-registry/extensions/NV/
DNV_vertex_program1_1.txt51 RCC, SUB, and ABS).
84 Should this extension provide SUB and ABS instructions even though
87 RESOLUTION: Yes. SUB and ABS provide no functionality that could
88 not be accomplished in VP1.0 with ADD and MAX idioms, SUB and ABS
160 SUB v,v v subtract
167 Add four new sections describing the DPH, RCC, SUB, and ABS
248 2.14.1.10.20 SUB: Subtract
250 The SUB instruction subtracts the values of the one source vector
297 Version 1.1 vertex programs provide support for the DPH, RCC, SUB,
338 | "SUB"
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/third_party/openGLES/extensions/NV/
DNV_vertex_program1_1.txt51 RCC, SUB, and ABS).
84 Should this extension provide SUB and ABS instructions even though
87 RESOLUTION: Yes. SUB and ABS provide no functionality that could
88 not be accomplished in VP1.0 with ADD and MAX idioms, SUB and ABS
160 SUB v,v v subtract
167 Add four new sections describing the DPH, RCC, SUB, and ABS
248 2.14.1.10.20 SUB: Subtract
250 The SUB instruction subtracts the values of the one source vector
297 Version 1.1 vertex programs provide support for the DPH, RCC, SUB,
338 | "SUB"
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/third_party/typescript/tests/arkTSTest/testcase/arkts-no-enum-mixed-types/
Darkts-no-enum-mixed-types-4-ok.ets22 SUB
36 case Operator.SUB:
Darkts-no-enum-mixed-types-4-error.ets22 SUB
36 case Operator.SUB:
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCISelDAGToDAG.cpp91 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB && in SelectAddrModeS9()
107 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeS9()
136 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeFar()
/third_party/toybox/toys/pending/
Dexpr.c132 enum { OR = 1, AND, EQ, NE, GT, GTE, LT, LTE, ADD, SUB, MUL, DIVI, MOD, RE }; enumerator
147 {"+", 4, I_TO_I, ADD }, {"-", 4, I_TO_I, SUB },
193 case SUB: x = a - b; break; in eval_op()
/third_party/mesa3d/src/nouveau/codegen/
Dnv50_ir_lowering_gm107.cpp231 qop = QUADOP(SUB, SUBR, SUB, SUBR); in handleDFDX()
235 qop = QUADOP(SUB, SUB, SUBR, SUBR); in handleDFDX()
/third_party/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-sub.txt6 SUB OUT[0], IN[0], IN[0].yzxw
Dfrag-srcmod-neg.txt8 SUB TEMP[0], IN[0], IN[0].yzxw
Dfrag-rcp.txt13 SUB OUT[0], TEMP[0], IMM[1]
Dfrag-rsq.txt13 SUB OUT[0], TEMP[0], IMM[1]
/third_party/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-sub.txt10 SUB OUT[0], IN[0], IMM[0]
Dvert-rcp.txt15 SUB OUT[0], TEMP[0], IMM[1]

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