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Searched refs:SchedClass (Results 1 – 23 of 23) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCSchedule.cpp57 unsigned SchedClass) const { in computeInstrLatency()
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency() local
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in computeInstrLatency()
78 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
81 if (SchedClass) in computeInstrLatency()
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput() local
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in getReciprocalThroughput()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h19 inline bool is_TC3x(unsigned SchedClass) { in is_TC3x() argument
20 switch (SchedClass) { in is_TC3x()
46 inline bool is_TC2early(unsigned SchedClass) { in is_TC2early() argument
47 switch (SchedClass) { in is_TC2early()
56 inline bool is_TC4x(unsigned SchedClass) { in is_TC4x() argument
57 switch (SchedClass) { in is_TC4x()
71 inline bool is_TC2(unsigned SchedClass) { in is_TC2() argument
72 switch (SchedClass) { in is_TC2()
100 inline bool is_TC1(unsigned SchedClass) { in is_TC1() argument
101 switch (SchedClass) { in is_TC1()
DHexagonInstrInfo.cpp2154 unsigned SchedClass = MI.getDesc().getSchedClass(); in isEarlySourceInstr() local
2155 return is_TC4x(SchedClass) || is_TC3x(SchedClass); in isEarlySourceInstr()
2346 unsigned SchedClass = MI.getDesc().getSchedClass(); in isLateResultInstr() local
2347 return !is_TC1(SchedClass); in isLateResultInstr()
2595 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1() local
2596 return is_TC1(SchedClass); in isTC1()
2600 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2() local
2601 return is_TC2(SchedClass); in isTC2()
2605 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early() local
2606 return is_TC2early(SchedClass); in isTC2Early()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetSchedule.cpp135 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() local
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
146 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
147 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
327 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput() local
328 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
340 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput() local
342 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
345 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
DMachinePipeliner.cpp917 unsigned SchedClass = Inst->getDesc().getSchedClass(); in minFuncUnits() local
921 make_range(InstrItins->beginStage(SchedClass), in minFuncUnits()
922 InstrItins->endStage(SchedClass))) { in minFuncUnits()
934 STI->getSchedModel().getSchedClassDesc(SchedClass); in minFuncUnits()
964 unsigned SchedClass = MI.getDesc().getSchedClass(); in calcCriticalResources() local
967 make_range(InstrItins->beginStage(SchedClass), in calcCriticalResources()
968 InstrItins->endStage(SchedClass))) { in calcCriticalResources()
977 STI->getSchedModel().getSchedClassDesc(SchedClass); in calcCriticalResources()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.h122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
124 return SU->SchedClass; in getSchedClass()
DSystemZScheduleZEC12.td106 // resources that it needs. These will be combined into a SchedClass.
DSystemZScheduleZ196.td103 // resources that it needs. These will be combined into a SchedClass.
DSystemZScheduleZ13.td122 // resources that it needs. These will be combined into a SchedClass.
DSystemZScheduleZ14.td122 // resources that it needs. These will be combined into a SchedClass.
DSystemZScheduleZ15.td122 // resources that it needs. These will be combined into a SchedClass.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h266 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
267 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
268 return SU->SchedClass; in getSchedClass()
DTargetSubtargetInfo.h139 virtual unsigned resolveSchedClass(unsigned SchedClass, in resolveSchedClass() argument
DScheduleDAG.h253 const MCSchedClassDesc *SchedClass = variable
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrDesc.h194 unsigned short SchedClass; // enum identifying instr sched class variable
619 unsigned getSchedClass() const { return SchedClass; } in getSchedClass()
DMCSchedule.h367 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
DMCSubtargetInfo.h214 resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, in resolveVariantSchedClass() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp402 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits() local
403 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); in getUnits()
413 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots() local
419 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots()
420 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc3755 unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
3773 unsigned resolveVariantSchedClass(unsigned SchedClass,
3775 return Mips_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
3864 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
3870 …unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel…
3871 …unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const ove…
3896 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel…
3897 switch (SchedClass) {
4059 report_fatal_error("Expected a variant SchedClass");
4063 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenSubtargetInfo.inc8075 unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
8093 unsigned resolveVariantSchedClass(unsigned SchedClass,
8095 return PPC_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
8212 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
8218 …unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel…
8219 …unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const ove…
8247 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel…
8248 report_fatal_error("Expected a variant SchedClass");
8252 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
8253 return PPC_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc18287 unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
18289 switch (SchedClass) {
19337 unsigned resolveVariantSchedClass(unsigned SchedClass,
19339 return ARM_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
19552 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
19558 …unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel…
19559 …unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const ove…
19587 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel…
19596 switch (SchedClass) {
23180 report_fatal_error("Expected a variant SchedClass");
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc21669 unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
21671 switch (SchedClass) {
23069 unsigned resolveVariantSchedClass(unsigned SchedClass,
23071 return X86_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
23239 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
23245 …unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel…
23246 …unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const ove…
23274 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel…
23275 switch (SchedClass) {
24657 report_fatal_error("Expected a variant SchedClass");
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc13758 unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
13760 switch (SchedClass) {
19158 unsigned resolveVariantSchedClass(unsigned SchedClass,
19160 return AArch64_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
19354 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
19360 …unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel…
19361 …unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const ove…
19386 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel…
19392 switch (SchedClass) {
24925 report_fatal_error("Expected a variant SchedClass");
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