| /third_party/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 2360 abs(vform, result, zn).SignedSaturate(vform); in Simulator()
2363 neg(vform, result, zn).SignedSaturate(vform); in Simulator()
3288 add(vform, result, zdn, zm).SignedSaturate(vform); in Simulator()
3291 sub(vform, result, zdn, zm).SignedSaturate(vform); in Simulator()
3294 sub(vform, result, zm, zdn).SignedSaturate(vform); in Simulator()
6736 abs(vf, rd, rn).SignedSaturate(vf); in Simulator()
6739 neg(vf, rd, rn).SignedSaturate(vf); in Simulator()
7293 add(vf, rd, rn, rm).SignedSaturate(vf); in Simulator()
7299 sub(vf, rd, rn, rm).SignedSaturate(vf); in Simulator()
7311 sshl(vf, rd, rn, rm).SignedSaturate(vf); in Simulator()
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| D | logic-aarch64.cc | 1674 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform); in sqshl()
1991 neg(vform, temp, src2).SignedSaturate(vform); in sshr()
2002 neg(vform, temp, src2).SignedSaturate(vform); in ushr()
2259 return extractnarrow(vform, dst, true, src, true).SignedSaturate(vform); in sqxtn()
2718 sub(vform, src1_r, src1_r, src2_i).SignedSaturate(vform); in cadd()
2719 add(vform, src1_i, src1_i, src2_r).SignedSaturate(vform); in cadd()
2727 add(vform, src1_r, src1_r, src2_i).SignedSaturate(vform); in cadd()
2728 sub(vform, src1_i, src1_i, src2_r).SignedSaturate(vform); in cadd()
3875 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal()
3894 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl()
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| D | simulator-aarch64.h | 703 LogicVRegister& SignedSaturate(VectorFormat vform) { in SignedSaturate() function
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-arm64.cc | 3960 abs(vf, rd, rn).SignedSaturate(vf); in VisitNEON2RegMisc()
3963 neg(vf, rd, rn).SignedSaturate(vf); in VisitNEON2RegMisc()
4377 add(vf, rd, rn, rm).SignedSaturate(vf); in VisitNEON3Same()
4383 sub(vf, rd, rn, rm).SignedSaturate(vf); in VisitNEON3Same()
4395 sshl(vf, rd, rn, rm).SignedSaturate(vf); in VisitNEON3Same()
4407 sshl(vf, rd, rn, rm).Round(vf).SignedSaturate(vf); in VisitNEON3Same()
5367 abs(vf, rd, rn).SignedSaturate(vf); in VisitNEONScalar2RegMisc()
5373 neg(vf, rd, rn).SignedSaturate(vf); in VisitNEONScalar2RegMisc()
5580 add(vf, rd, rn, rm).SignedSaturate(vf); in VisitNEONScalar3Same()
5586 sub(vf, rd, rn, rm).SignedSaturate(vf); in VisitNEONScalar3Same()
[all …]
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| D | simulator-logic-arm64.cc | 1414 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform); in sqshl()
1816 return ExtractNarrow(vform, dst, true, src, true).SignedSaturate(vform); in sqxtn()
2678 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal()
2686 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal2()
2694 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl()
2702 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl2()
2710 return add(vform, dst, product, product).SignedSaturate(vform); in sqdmull()
2718 return add(vform, dst, product, product).SignedSaturate(vform); in sqdmull2()
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| D | simulator-arm64.h | 562 LogicVRegister& SignedSaturate(VectorFormat vform) { in SignedSaturate() function
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