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Searched refs:Src0RC (Results 1 – 4 of 4) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1593 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1594 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1595 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1600 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1613 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1618 (ins Src0RC:$src0, clampmod0:$clamp),
1619 (ins Src0RC:$src0))
1625 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1628 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1634 (ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
[all …]
DSIFixSGPRCopies.cpp676 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
678 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
681 (TRI->hasVectorRegisters(Src0RC) || in runOnMachineFunction()
DSIInstrInfo.cpp4635 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
4636 if (DstRC != Src0RC) { in legalizeOperands()
5308 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
5312 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
5314 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
5324 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
5371 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); in splitScalar64BitAddSub() local
5373 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
5376 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub()
5382 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub()
[all …]
DAMDGPUInstructionSelector.cpp612 const TargetRegisterClass *Src0RC = in selectG_INSERT() local
619 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg); in selectG_INSERT()
620 if (!Src0RC) in selectG_INSERT()
624 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT()