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Searched refs:SrcOp1 (Results 1 – 5 of 5) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp1772 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); in getShuffleComment() local
1777 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; in getShuffleComment()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4131 auto &SrcOp1 = Operands[OpndNum1];
4133 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4134 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4906 auto &SrcOp1 = Operands[OpndNum1];
4908 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4909 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12455 auto &SrcOp1 = Operands[OpndNum1];
12457 if (SrcOp1->isReg() && SrcOp2->isReg()) {
12458 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc7592 auto &SrcOp1 = Operands[OpndNum1];
7594 if (SrcOp1->isReg() && SrcOp2->isReg()) {
7595 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {