Home
last modified time | relevance | path

Searched refs:SrcReg (Results 1 – 25 of 201) sorted by relevance

123456789

/third_party/mesa3d/src/mesa/program/
Dprogramopt.c93 newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR; in insert_mvp_dp4_code()
94 newInst[i].SrcReg[0].Index = mvpRef[i]; in insert_mvp_dp4_code()
95 newInst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP; in insert_mvp_dp4_code()
96 newInst[i].SrcReg[1].File = PROGRAM_INPUT; in insert_mvp_dp4_code()
97 newInst[i].SrcReg[1].Index = VERT_ATTRIB_POS; in insert_mvp_dp4_code()
98 newInst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP; in insert_mvp_dp4_code()
164 newInst[0].SrcReg[0].File = PROGRAM_INPUT; in insert_mvp_mad_code()
165 newInst[0].SrcReg[0].Index = VERT_ATTRIB_POS; in insert_mvp_mad_code()
166 newInst[0].SrcReg[0].Swizzle = SWIZZLE_XXXX; in insert_mvp_mad_code()
167 newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR; in insert_mvp_mad_code()
[all …]
Dprog_parameter_layout.c159 if (inst->SrcReg[i].Base.RelAddr) { in _mesa_layout_parameters()
162 if (!inst->SrcReg[i].Symbol->pass1_done) { in _mesa_layout_parameters()
165 inst->SrcReg[i].Symbol->param_binding_begin, in _mesa_layout_parameters()
166 inst->SrcReg[i].Symbol->param_binding_length); in _mesa_layout_parameters()
173 inst->SrcReg[i].Symbol->param_binding_begin = new_begin; in _mesa_layout_parameters()
174 inst->SrcReg[i].Symbol->pass1_done = 1; in _mesa_layout_parameters()
181 inst->Base.SrcReg[i] = inst->SrcReg[i].Base; in _mesa_layout_parameters()
182 inst->Base.SrcReg[i].Index += in _mesa_layout_parameters()
183 inst->SrcReg[i].Symbol->param_binding_begin; in _mesa_layout_parameters()
193 const int idx = inst->SrcReg[i].Base.Index; in _mesa_layout_parameters()
[all …]
/third_party/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_program_tex.c70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in scale_texcoords()
71 inst_mov->U.I.SrcReg[1].File = RC_FILE_CONSTANT; in scale_texcoords()
72 inst_mov->U.I.SrcReg[1].Index = in scale_texcoords()
76 reset_srcreg(&inst->U.I.SrcReg[0]); in scale_texcoords()
77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in scale_texcoords()
78 inst->U.I.SrcReg[0].Index = temp; in scale_texcoords()
93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
96 inst_rcp->U.I.SrcReg[0].Swizzle = in projective_divide()
97 RC_MAKE_SWIZZLE_SMEAR(GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 3)); in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
[all …]
Dradeon_optimize.c78 &reader_data->Writer->U.I.PreSub.SrcReg[0], in copy_propagate_scan_read()
79 &reader_data->Writer->U.I.PreSub.SrcReg[1])) { in copy_propagate_scan_read()
93 if(reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_TEMPORARY && in copy_propagate_scan_read()
94 reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_INPUT && in copy_propagate_scan_read()
168 inst->U.I.SrcReg[0].File == RC_FILE_PRESUB || in copy_propagate()
169 inst->U.I.SrcReg[0].Abs || in copy_propagate()
170 inst->U.I.SrcReg[0].Negate) { in copy_propagate()
179 …_data.Readers[i].U.I.Src = chain_srcregs(*reader_data.Readers[i].U.I.Src, inst_mov->U.I.SrcReg[0]); in copy_propagate()
181 if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB) in copy_propagate()
234 if (is_src_uniform_constant(inst->U.I.SrcReg[2], &swz, &negate)) { in constant_folding_mad()
[all …]
Dr3xx_vertprog.c45 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
50 t_src_class(vpi->SrcReg[x].File), \
51 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
200 inst[1] = t_src(vp, &vpi->SrcReg[0]); in ei_vector1()
217 inst[1] = t_src(vp, &vpi->SrcReg[0]); in ei_vector2()
218 inst[2] = t_src(vp, &vpi->SrcReg[1]); in ei_vector2()
234 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]); in ei_math1()
253 …inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizz… in ei_lit()
254 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W in ei_lit()
256 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y in ei_lit()
[all …]
Dradeon_pair_translate.c46 inst->SrcReg[2] = inst->SrcReg[1]; in final_rewrite()
47 inst->SrcReg[1].File = RC_FILE_NONE; in final_rewrite()
48 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111; in final_rewrite()
49 inst->SrcReg[1].Negate = RC_MASK_NONE; in final_rewrite()
53 tmp = inst->SrcReg[2]; in final_rewrite()
54 inst->SrcReg[2] = inst->SrcReg[0]; in final_rewrite()
55 inst->SrcReg[0] = tmp; in final_rewrite()
68 inst->SrcReg[1].File = RC_FILE_NONE; in final_rewrite()
69 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111; in final_rewrite()
70 inst->SrcReg[2].File = RC_FILE_NONE; in final_rewrite()
[all …]
Dradeon_compiler.c128 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT) in rc_calculate_inputs_outputs()
129 c->Program.InputsRead |= 1U << inst->U.I.SrcReg[i].Index; in rc_calculate_inputs_outputs()
200 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in rc_copy_output()
201 inst->U.I.SrcReg[0].Index = tempreg; in rc_copy_output()
202 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; in rc_copy_output()
209 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in rc_copy_output()
210 inst->U.I.SrcReg[0].Index = tempreg; in rc_copy_output()
211 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; in rc_copy_output()
241 inst_rcp->U.I.SrcReg[0].File = RC_FILE_INPUT; in rc_transform_fragment_wpos()
242 inst_rcp->U.I.SrcReg[0].Index = new_input; in rc_transform_fragment_wpos()
[all …]
Dradeon_program_alu.c46 struct rc_dst_register DstReg, struct rc_src_register SrcReg) in emit1() argument
56 fpi->U.I.SrcReg[0] = SrcReg; in emit1()
74 fpi->U.I.SrcReg[0] = SrcReg0; in emit2()
75 fpi->U.I.SrcReg[1] = SrcReg1; in emit2()
94 fpi->U.I.SrcReg[0] = SrcReg0; in emit3()
95 fpi->U.I.SrcReg[1] = SrcReg1; in emit3()
96 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
209 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY && in is_dst_safe_to_reuse()
210 inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index) in is_dst_safe_to_reuse()
244 emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, negate(inst->U.I.SrcReg[0])); in transform_CEIL()
[all …]
Dradeon_vert_fc.c130 new_inst->U.I.SrcReg[0].Index = 0; in lower_bgnloop()
131 new_inst->U.I.SrcReg[0].File = RC_FILE_NONE; in lower_bgnloop()
132 new_inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000; in lower_bgnloop()
140 build_pred_src(&new_inst->U.I.SrcReg[0], fc_state); in lower_bgnloop()
150 new_inst->U.I.SrcReg[1].Index = 0; in lower_bgnloop()
151 new_inst->U.I.SrcReg[1].File = RC_FILE_NONE; in lower_bgnloop()
152 new_inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_0000; in lower_bgnloop()
164 inst->U.I.SrcReg[0].Index = 0; in lower_brk()
165 inst->U.I.SrcReg[0].File = RC_FILE_NONE; in lower_brk()
166 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000; in lower_brk()
[all …]
Dradeon_emulate_branches.c79 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in handle_if()
81 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in handle_if()
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; in handle_if()
83 inst->U.I.SrcReg[0].Swizzle = 0; in handle_if()
84 inst->U.I.SrcReg[0].Abs = 0; in handle_if()
85 inst->U.I.SrcReg[0].Negate = 0; in handle_if()
169 inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in allocate_and_insert_proxies()
170 inst_mov->U.I.SrcReg[0].Index = index; in allocate_and_insert_proxies()
188 inst_cmp->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0]; in inject_cmp()
189 inst_cmp->U.I.SrcReg[0].Abs = 1; in inject_cmp()
[all …]
Dradeon_dataflow_swizzles.c49 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED) in rewrite_source()
53 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split); in rewrite_source()
63 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src]; in rewrite_source()
68 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED); in rewrite_source()
71 masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate; in rewrite_source()
73 mov->U.I.SrcReg[0].Negate = 0; in rewrite_source()
75 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW; in rewrite_source()
79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY; in rewrite_source()
80 inst->U.I.SrcReg[src].Index = tempreg; in rewrite_source()
81 inst->U.I.SrcReg[src].Swizzle = 0; in rewrite_source()
[all …]
Dradeon_program_print.c204 rc_print_register(f, inst.SrcReg[0].File, in rc_print_presub_instruction()
205 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); in rc_print_presub_instruction()
208 rc_print_register(f, inst.SrcReg[1].File, in rc_print_presub_instruction()
209 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); in rc_print_presub_instruction()
211 rc_print_register(f, inst.SrcReg[0].File, in rc_print_presub_instruction()
212 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); in rc_print_presub_instruction()
215 rc_print_register(f, inst.SrcReg[1].File, in rc_print_presub_instruction()
216 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); in rc_print_presub_instruction()
218 rc_print_register(f, inst.SrcReg[0].File, in rc_print_presub_instruction()
219 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); in rc_print_presub_instruction()
[all …]
Dr500_fragprog.c57 var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]); in r500_transform_IF()
100 if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) { in r500_transform_IF()
114 inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0]; in r500_transform_IF()
116 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4( in r500_transform_IF()
117 inst_mov->U.I.SrcReg[0].Swizzle, in r500_transform_IF()
121 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4( in r500_transform_IF()
122 inst_mov->U.I.SrcReg[0].Swizzle, in r500_transform_IF()
166 temp_src = writer->Inst->U.I.SrcReg[0]; in r500_transform_IF()
167 writer->Inst->U.I.SrcReg[0] = in r500_transform_IF()
168 writer->Inst->U.I.SrcReg[1]; in r500_transform_IF()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.h26 inline static unsigned getCRFromCRBit(unsigned SrcReg) { in getCRFromCRBit() argument
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) in getCRFromCRBit()
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || in getCRFromCRBit()
[all …]
DPPCFastISel.cpp155 unsigned SrcReg, unsigned Flag = 0, in copyRegToRegClass() argument
159 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass()
168 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
172 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
183 unsigned SrcReg, bool IsSigned);
184 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
624 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore() argument
625 assert(SrcReg && "Nothing to store!"); in PPCEmitStore()
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore()
688 .addReg(SrcReg) in PPCEmitStore()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp140 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
143 Register::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
147 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
161 Register SrcReg = Src2.getReg(); in runOnMachineFunction() local
162 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
178 Register SrcReg = Src1.getReg(); in runOnMachineFunction() local
180 std::make_pair(*&SrcReg, Hexagon::isub_hi); in runOnMachineFunction()
189 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
192 Register::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
196 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp41 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
49 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
52 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
62 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
70 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
83 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
87 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
97 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
203 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
207 if (HexagonMCInstrInfo::isIntReg(SrcReg) && in getDuplexCandidateGroup()
208 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
212 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
221 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
223 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
242 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
244 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
252 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp34 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
47 Register SrcReg = MI->getOperand(1).getReg(); in expandMEMCPY() local
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp308 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
323 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
331 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
335 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp146 Register SrcReg = MI.getOperand(2).getReg(); in expandArith() local
151 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
179 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic() local
184 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLogic()
423 unsigned SrcReg = MI.getOperand(1).getReg(); in expand() local
429 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
456 unsigned SrcReg = MI.getOperand(1).getReg(); in expand() local
462 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
585 unsigned SrcReg = MI.getOperand(1).getReg(); in expand() local
592 if (DstReg == SrcReg) in expand()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp86 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
96 } else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
98 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg()
100 else if (Mips::HI32RegClass.contains(SrcReg)) { in copyPhysReg()
102 SrcReg = 0; in copyPhysReg()
103 } else if (Mips::LO32RegClass.contains(SrcReg)) { in copyPhysReg()
105 SrcReg = 0; in copyPhysReg()
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) in copyPhysReg()
108 else if (Mips::LO32DSPRegClass.contains(SrcReg)) in copyPhysReg()
[all …]
DMipsFastISel.cpp183 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
185 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
219 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg, in emitInstStore() argument
221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DPHIElimination.cpp376 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg(); in LowerPHINode() local
379 isImplicitlyDefined(SrcReg, *MRI); in LowerPHINode()
380 assert(Register::isVirtualRegister(SrcReg) && in LowerPHINode()
396 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); in LowerPHINode()
410 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode()
416 SrcReg, SrcSubReg, IncomingReg); in LowerPHINode()
424 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && in LowerPHINode()
425 !LV->isLiveOut(SrcReg, opBlock)) { in LowerPHINode()
446 if (Term->readsRegister(SrcReg)) in LowerPHINode()
460 if (KillInst->readsRegister(SrcReg)) in LowerPHINode()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h55 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt() local
59 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
63 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
70 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
82 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
104 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt() local
108 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineZExt()
114 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
120 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt()
126 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt()
[all …]

123456789