| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 178 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = 0; in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
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| D | LanaiInstrInfo.h | 98 unsigned &SrcReg2, int &CmpMask,
105 unsigned SrcReg2, int CmpMask, int CmpValue,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 631 Register SrcReg2 = in fuseCompareOperations() local
636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
688 if (SrcReg2) in fuseCompareOperations()
689 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
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| D | SystemZInstrInfo.h | 223 unsigned &SrcReg2, int &Mask, int &Value) const override;
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| D | SystemZInstrInfo.cpp | 517 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
524 SrcReg2 = 0; in analyzeCompare()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 857 unsigned SrcReg2 = 0; in PPCEmitCmp() local
859 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
860 if (SrcReg2 == 0) in PPCEmitCmp()
868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp()
891 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2); in PPCEmitCmp()
941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
943 SrcReg2 = ExtReg; in PPCEmitCmp()
949 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1359 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1360 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
[all …]
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| D | PPCInstrInfo.h | 352 unsigned &SrcReg2, int &Mask, int &Value) const override;
355 unsigned SrcReg2, int Mask, int Value,
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| D | PPCInstrInfo.cpp | 1591 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
1602 SrcReg2 = 0; in analyzeCompare()
1613 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1621 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
1727 if (SrcReg2 != 0) in optimizeCompareInstr()
1802 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1803 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1849 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
4125 Register SrcReg2 = MI.getOperand(2).getReg(); in isSignOrZeroExtended() local
4128 !Register::isVirtualRegister(SrcReg2)) in isSignOrZeroExtended()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 209 unsigned &SrcReg2, int &CmpMask,
214 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | AArch64SIMDInstrOpt.cpp | 438 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
444 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
447 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
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| D | AArch64InstrInfo.cpp | 988 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
1013 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1022 SrcReg2 = 0; in analyzeCompare()
1032 SrcReg2 = 0; in analyzeCompare()
1183 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
1213 if (CmpValue != 0 || SrcReg2 != 0) in optimizeCompareInstr()
4184 unsigned SrcReg2; in genFusedMultiply() local
4188 SrcReg2 = *ReplacedAddend; in genFusedMultiply()
4191 SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); in genFusedMultiply()
4201 if (Register::isVirtualRegister(SrcReg2)) in genFusedMultiply()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1428 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1430 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1431 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1440 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1449 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1777 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
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| D | ARMBaseInstrInfo.cpp | 2675 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
2683 SrcReg2 = 0; in analyzeCompare()
2691 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
2698 SrcReg2 = 0; in analyzeCompare()
2746 unsigned SrcReg, unsigned SrcReg2, in isRedundantFlagInstr() argument
2752 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2753 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2761 OI->getOperand(3).getReg() == SrcReg2) || in isRedundantFlagInstr()
2762 (OI->getOperand(2).getReg() == SrcReg2 && in isRedundantFlagInstr()
2789 OI->getOperand(1).getReg() == SrcReg2) { in isRedundantFlagInstr()
[all …]
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| D | ARMBaseInstrInfo.h | 290 unsigned &SrcReg2, int &CmpMask,
298 unsigned SrcReg2, int CmpMask, int CmpValue,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 473 unsigned &SrcReg2, int &CmpMask,
480 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | X86InstrInfo.cpp | 1053 Register SrcReg2; in convertToThreeAddress() local
1056 SrcReg2, isKill2, ImplicitOp2, LV)) in convertToThreeAddress()
1065 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
1067 LV->replaceKillInstruction(SrcReg2, MI, *NewMI); in convertToThreeAddress()
3274 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
3286 SrcReg2 = 0; in analyzeCompare()
3300 SrcReg2 = 0; in analyzeCompare()
3309 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
3321 SrcReg2 = 0; in analyzeCompare()
3334 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 610 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
614 (SrcReg2 != 0 && Register::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1398 unsigned &SrcReg2, int &Mask, int &Value) const { in analyzeCompare() argument
1406 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 272 unsigned &SrcReg2, int &Mask, int &Value) const override;
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| D | HexagonInstrInfo.cpp | 1766 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
1827 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1842 SrcReg2 = 0; in analyzeCompare()
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 84 struct rc_src_register SrcReg2) in emit3() argument
96 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
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