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Searched refs:SubRegIdx (Results 1 – 25 of 25) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
DRegisterPressure.cpp534 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
537 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
542 SubRegIdx = 0; in collectOperandLanes()
546 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
548 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
552 void pushRegLanes(unsigned Reg, unsigned SubRegIdx, in pushRegLanes() argument
555 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
556 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1233 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1234 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
DVirtRegMap.cpp363 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
364 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
365 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
DStackMaps.cpp159 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
160 if (SubRegIdx) in parseOperand()
161 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
DRegAllocFast.cpp768 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
769 if (SubRegIdx != 0) { in allocVirtRegUndef()
770 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
DMachineVerifier.cpp1971 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1972 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1973 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2073 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
2074 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2075 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
DRegisterCoalescer.cpp298 MachineOperand &MO, unsigned SubRegIdx);
1655 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1656 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupBWInsts.cpp195 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
201 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
209 if (SubRegIdx != X86::sub_8bit) in getSuperRegDestIfDead()
DX86FlagsCopyLowering.cpp1002 int SubRegIdx[] = {X86::NoSubRegister, X86::sub_8bit, X86::sub_16bit, in rewriteSetCarryExtended() local
1025 .addImm(SubRegIdx[OrigRegSize]); in rewriteSetCarryExtended()
1034 .addReg(Reg, 0, SubRegIdx[TargetRegSize]); in rewriteSetCarryExtended()
DX86InstrAVX512.td93 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
3142 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3143 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3152 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3153 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3167 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3177 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3186 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3196 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3208 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
[all …]
DX86ISelDAGToDAG.cpp1323 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
1324 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
DX86InstrInfo.cpp7576 if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) { in describeMOVrrLoadedValue() local
7577 unsigned SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx); in describeMOVrrLoadedValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp1198 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeSBufferLoadImmPair() local
1199 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeSBufferLoadImmPair()
1200 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeSBufferLoadImmPair()
1260 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferLoadPair() local
1261 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeBufferLoadPair()
1262 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeBufferLoadPair()
1327 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferLoadPair() local
1328 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferLoadPair()
1329 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferLoadPair()
1357 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferStorePair() local
[all …]
DAMDGPUInstructionSelector.cpp1276 int SubRegIdx = sizeToSubRegIndex(DstSize); in selectG_TRUNC() local
1277 if (SubRegIdx == -1) in selectG_TRUNC()
1282 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); in selectG_TRUNC()
1286 I.getOperand(1).setSubReg(SubRegIdx); in selectG_TRUNC()
DAMDGPUISelDAGToDAG.cpp600 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); in getOperandRegClass() local
602 SubRegIdx); in getOperandRegClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h816 int64_t SubRegIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
819 0, SubRegIdx); in executeMatchTable()
823 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1730 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
1735 SubRegIdx), 0); in ExtendToInt64()
1744 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local
1746 MVT::i32, V, SubRegIdx), 0); in TruncateToInt32()
2813 SDValue SubRegIdx = in addExtOrTrunc() local
2816 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
2823 SDValue SubRegIdx = in addExtOrTrunc() local
2826 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp214 unsigned SubRegIdx);
216 unsigned SubRegIdx);
1280 unsigned SubRegIdx) { in SelectLoad() argument
1294 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1306 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1330 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
DAArch64InstrInfo.td2822 SubRegIndex SubRegIdx,
2827 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2832 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2950 SubRegIndex SubRegIdx, Operand IndexType,
2954 (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
3087 SubRegIndex SubRegIdx, Instruction STR> {
3088 defm : VecStoreLane0Pat<am_unscaled128, StoreOp, VTy, STy, SubRegIdx, simm9, STR>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp1167 unsigned SubRegIdx = in loadVectorConstant() local
1170 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp4061 SDValue SubRegIdx = in Select() local
4064 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); in Select()
4074 SDValue SubRegIdx = in Select() local
4077 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); in Select()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3341 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; in emitINSERT_DF_VIDX() local
3398 .addReg(LaneReg, 0, SubRegIdx); in emitINSERT_DF_VIDX()
3427 .addReg(LaneTmp2, 0, SubRegIdx); in emitINSERT_DF_VIDX()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc27046 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/7, // Rn
28723 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn
28752 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn
28781 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn
28810 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn
37908 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val
37941 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val
37974 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val
38007 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val
38040 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc3002 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src1
3022 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1
10677 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
10692 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
10708 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc12542 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
13278 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
14054 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
14810 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs