Searched refs:TEX_INST (Results 1 – 6 of 6) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 43 TEX_INST = (1 << 13), enumerator
62 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
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| D | R600OptimizeVectorRegisters.cpp | 153 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in canSwizzle()
267 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in SwizzleInput()
352 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { in runOnMachineFunction()
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| D | R600InstrFormats.td | 290 bits<5> TEX_INST;
300 let Word0{4-0} = TEX_INST;
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| D | R600Instructions.td | 945 let TEX_INST = inst{4-0};
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| /third_party/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_builder.cpp | 514 .TEX_INST(ctx.fetch_opcode(bc.op)); in build_fetch_tex()
524 .TEX_INST(ctx.fetch_opcode(bc.op)); in build_fetch_tex()
536 .TEX_INST(ctx.fetch_opcode(bc.op)); in build_fetch_tex()
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| D | sb_bc_fmt_def.inc | 482 BC_FIELD(TEX_WORD0, TEX_INST, T_INST, 4, 0)
493 BC_FIELD(TEX_WORD0, TEX_INST, T_INST, 4, 0)
505 BC_FIELD(TEX_WORD0, TEX_INST, T_INST, 4, 0)
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