| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) { in usesRegClass() argument
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
141 return TRC->contains(Reg); in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
435 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
436 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
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| D | ARMISelLowering.cpp | 9502 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local
9521 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9527 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9533 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9551 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9556 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9561 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9566 Register NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9572 Register NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
9587 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
[all …]
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| D | ARMLoadStoreOptimizer.cpp | 2330 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2331 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2332 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
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| D | ARMBaseInstrInfo.cpp | 3299 const TargetRegisterClass *TRC = MRI->getRegClass(Reg); in FoldImmediate() local
3300 Register NewReg = MRI->createVirtualRegister(TRC); in FoldImmediate()
3322 MRI->setRegClass(UseMI.getOperand(0).getReg(), TRC); in FoldImmediate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 499 const TargetRegisterClass *TRC = in EmitSubregNode() local
517 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
523 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
537 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
656 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
62 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
503 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
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| D | RegAllocPBQP.cpp | 604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
612 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
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| D | LiveDebugVariables.cpp | 1204 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
1205 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 1055 const TargetRegisterClass &TRC, in isOfRegClass() argument
1059 return RC == &TRC; in isOfRegClass()
1061 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AvoidStoreForwardingBlocks.cpp | 566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
568 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
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| D | X86ISelLowering.cpp | 31963 const TargetRegisterClass *TRC = in SetupEntryBlockForSjLj() local
31965 VR = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() argument
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| /third_party/gstreamer/gstplugins_base/ext/alsa/ |
| D | gstalsa.c | 746 ITEM (TRC, TOP_REAR_CENTER),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 776 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
779 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
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| D | PPCISelDAGToDAG.cpp | 321 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); in SelectInlineAsmMemoryOperand() local
323 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); in SelectInlineAsmMemoryOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1987 const TargetRegisterClass *TRC; in createVR() local
1989 TRC = &Hexagon::PredRegsRegClass; in createVR()
1991 TRC = &Hexagon::IntRegsRegClass; in createVR()
1993 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
1998 Register NewReg = MRI.createVirtualRegister(TRC); in createVR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1669 const TargetRegisterClass *TRC = in SelectInlineAsmMemoryOperand() local
1672 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); in SelectInlineAsmMemoryOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 316 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF); in SelectInlineAsmMemoryOperand() local
318 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64); in SelectInlineAsmMemoryOperand()
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| /third_party/alsa-lib/src/pcm/ |
| D | pcm.c | 8193 _NAME(TRL), _NAME(TRR), _NAME(TRC),
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| /third_party/openGLES/extensions/ARB/ |
| D | ARB_fragment_program.txt | 4951 - Removed TRC and MOD instructions.
5050 - Added TRC, POW, DPH instructions, updated FRC and LRP.
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| /third_party/skia/third_party/externals/opengl-registry/extensions/ARB/ |
| D | ARB_fragment_program.txt | 4941 - Removed TRC and MOD instructions.
5040 - Added TRC, POW, DPH instructions, updated FRC and LRP.
|