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Searched refs:Tmp1 (Results 1 – 24 of 24) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp366 SDValue Tmp1 = Vec; in PerformInsertVectorEltInMemory() local
376 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory()
384 DAG.getEntryNode(), dl, Tmp1, StackPtr, in PerformInsertVectorEltInMemory()
1591 SDValue Tmp1 = SDValue(Node, 0); in ExpandDYNAMIC_STACKALLOC() local
1594 SDValue Chain = Tmp1.getOperand(0); in ExpandDYNAMIC_STACKALLOC()
1606 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in ExpandDYNAMIC_STACKALLOC()
1608 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, in ExpandDYNAMIC_STACKALLOC()
1610 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain in ExpandDYNAMIC_STACKALLOC()
1615 Results.push_back(Tmp1); in ExpandDYNAMIC_STACKALLOC()
2425 SDValue Tmp1; in ExpandLegalINT_TO_FP() local
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DLegalizeFloatTypes.cpp1708 SDValue Tmp1, Tmp2, Tmp3; in FloatExpandSetCCOperands() local
1709 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), in FloatExpandSetCCOperands()
1713 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1714 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), in FloatExpandSetCCOperands()
1718 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1719 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
DSelectionDAG.cpp1939 SDValue Tmp1 = Node->getOperand(0); in expandVAArg() local
1943 SDValue VAListLoad = getLoad(TLI.getPointerTy(getDataLayout()), dl, Tmp1, in expandVAArg()
1957 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, in expandVAArg()
1962 Tmp1 = in expandVAArg()
1963 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); in expandVAArg()
1965 return getLoad(VT, dl, Tmp1, VAList, MachinePointerInfo()); in expandVAArg()
1975 SDValue Tmp1 = in expandVACopy() local
1978 return getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), in expandVACopy()
DSelectionDAGBuilder.cpp7590 SDValue Tmp1 = getValue(I.getArgOperand(1)); in visitBinaryFloatCall() local
7592 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1)); in visitBinaryFloatCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DIntrinsicLowering.cpp64 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
68 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
78 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
87 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
108 Value* Tmp1 = Builder.CreateLShr(V, in LowerBSWAP() local
138 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp131 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode() local
134 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode()
135 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
136 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp); in generateSignedDivisionCode()
255 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode() local
256 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp3609 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3610 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
3612 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
3645 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3646 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
3647 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
3678 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
3679 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
3680 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4226 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Load; in tryVPTESTM() local
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DX86ISelLowering.cpp18495 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, in LowerShiftParts() local
18519 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in LowerShiftParts()
18522 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in LowerShiftParts()
32753 unsigned Tmp0 = SrcBits, Tmp1 = SrcBits; in ComputeNumSignBitsForTargetNode() local
32757 Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), DemandedRHS, Depth + 1); in ComputeNumSignBitsForTargetNode()
32758 unsigned Tmp = std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
32797 unsigned Tmp1 = in ComputeNumSignBitsForTargetNode() local
32799 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
32805 unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth+1); in ComputeNumSignBitsForTargetNode() local
32806 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp387 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
389 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
403 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
405 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
409 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
413 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
415 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUPromoteAlloca.cpp817 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ, "", true, true); in handleAlloca() local
818 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
DAMDGPUCodeGenPrepare.cpp846 Value *Tmp1 = Builder.CreateAnd(Remainder_GE_Den, Remainder_GE_Zero); in expandDivRem32() local
847 Value *Tmp1_0_CC = Builder.CreateICmpEQ(Tmp1, Zero); in expandDivRem32()
DAMDGPULegalizerInfo.cpp1372 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign); in legalizeFrint() local
1373 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFrint()
1469 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc() local
1470 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
DAMDGPUISelLowering.cpp1920 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, in LowerUDIVREM() local
1934 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT), in LowerUDIVREM()
1950 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT), in LowerUDIVREM()
2122 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC() local
2123 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2140 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT() local
2141 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2226 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT, in LowerFROUND64() local
2230 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1, in LowerFROUND64()
DSIISelLowering.cpp9069 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine() local
9073 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3); in performIntMed3ImmCombine()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp1877 SmallVector<MachineOperand,2> Tmp1; in createPreheaderForLoop() local
1880 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) in createPreheaderForLoop()
1885 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false); in createPreheaderForLoop()
DHexagonSplitDouble.cpp693 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4/*size*/, A); in splitMemRef() local
694 LowI->addMemOperand(MF, Tmp1); in splitMemRef()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/lib/Support/
DAPInt.cpp736 unsigned Tmp1 = unsigned(VAL >> 16); in byteSwap() local
737 Tmp1 = ByteSwap_32(Tmp1); in byteSwap()
740 return APInt(BitWidth, (uint64_t(Tmp2) << 32) | Tmp1); in byteSwap()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
DAPInt.cpp679 unsigned Tmp1 = unsigned(U.VAL >> 16); in byteSwap() local
680 Tmp1 = ByteSwap_32(Tmp1); in byteSwap()
683 return APInt(BitWidth, (uint64_t(Tmp2) << 32) | Tmp1); in byteSwap()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp2000 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts() local
2004 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2060 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts() local
2064 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
2415 SDValue Tmp1 = ST->getChain(); in LowerSTOREi1() local
2421 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp5503 SDValue Tmp1 = Op.getOperand(1); in LowerFCOPYSIGN() local
5506 EVT SrcVT = Tmp1.getValueType(); in LowerFCOPYSIGN()
5524 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
5526 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN()
5527 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
5530 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, in LowerFCOPYSIGN()
5531 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
5534 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
5543 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), in LowerFCOPYSIGN()
5558 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp5269 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
5272 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), in Select()
5283 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
5286 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), in Select()
DPPCISelLowering.cpp8373 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSHL_PARTS() local
8376 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS()
8402 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRL_PARTS() local
8405 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS()
8430 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRA_PARTS() local
8433 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2964 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO() local
2965 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp7400 Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass); in emitPair128() local
7403 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1); in emitPair128()
7405 .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64); in emitPair128()