Searched refs:UMULO (Results 1 – 16 of 16) sorted by relevance
258 SMULO, UMULO, enumerator
146 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()1153 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()1903 case ISD::UMULO: in ExpandIntegerResult()3040 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()3518 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()3545 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow); in ExpandIntRes_XMULO()3550 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow); in ExpandIntRes_XMULO()
453 case ISD::UMULO: in LegalizeOp()942 case ISD::UMULO: in Expand()
297 case ISD::UMULO: return "umulo"; in getOperationName()
160 case ISD::UMULO: in ScalarizeVectorResult()955 case ISD::UMULO: in SplitVectorResult()2766 case ISD::UMULO: in WidenVectorResult()
2846 case ISD::UMULO: in computeKnownBits()3736 case ISD::UMULO: in ComputeNumSignBits()9330 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
7211 } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) { in expandFixedPointMul()7213 DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()
3498 case ISD::UMULO: in ExpandNode()
6640 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; in visitIntrinsicCall()
1531 case ISD::UMULO: return visitMULO(N); in visit()
324 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; in mightUseCTR()
1674 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()3056 case ISD::UMULO: in LowerOperation()
670 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
383 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()384 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()2235 case ISD::UMULO: { in getAArch64XALUOOp()2340 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); in isOverflowIntrOpRes()3194 case ISD::UMULO: in LowerOperation()
4437 case ISD::UMULO: in getARMXALUOOp()5218 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()5269 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
1932 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()21992 case ISD::UMULO: in getX86XALUOOp()22278 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()22834 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()22886 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerBRCOND()28636 case ISD::UMULO: return LowerXALUO(Op, DAG); in LowerOperation()