| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 690 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
694 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
698 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
702 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
707 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
711 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
715 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
719 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
980 case ISD::UREM: in isHardwareLoopProfitable()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiTargetTransformInfo.h | 95 case ISD::UREM:
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| D | LanaiISelLowering.cpp | 111 setOperationAction(ISD::UREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 249 ISD == ISD::UREM) && in getArithmeticInstrCost()
353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
411 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1936 case ISD::UREM: in selectDivRem()
1953 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2058 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2059 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
|
| D | MipsSEISelLowering.cpp | 243 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
290 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
348 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
2064 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 700 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
|
| D | SelectionDAGDumper.cpp | 233 case ISD::UREM: return "urem"; in getOperationName()
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| D | FastISel.cpp | 641 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
1821 return selectBinaryOp(I, ISD::UREM); in selectOperator()
|
| D | LegalizeDAG.cpp | 3275 case ISD::UREM: in ExpandNode()
4154 case ISD::UREM: in ConvertNodeToLibcall()
4326 case ISD::UREM: in PromoteNode()
4346 case ISD::UREM: in PromoteNode()
|
| D | SelectionDAG.cpp | 3207 case ISD::UREM: { in computeKnownBits()
4814 case ISD::UREM: in FoldValue()
4866 case ISD::UREM: { in isUndef()
5193 case ISD::UREM: in getNode()
5472 case ISD::UREM: in getNode()
5494 case ISD::UREM: in getNode()
|
| D | LegalizeVectorOps.cpp | 374 case ISD::UREM: in LegalizeOp()
|
| D | LegalizeVectorTypes.cpp | 139 case ISD::UREM: in ScalarizeVectorResult()
928 case ISD::UREM: in SplitVectorResult()
2743 case ISD::UREM: in WidenVectorResult()
|
| D | TargetLowering.cpp | 3542 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() && in SimplifySetCC()
3927 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && in SimplifySetCC()
3934 if (N0.getOpcode() == ISD::UREM) { in SimplifySetCC()
5961 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 132 setOperationAction(ISD::UREM, XLenVT, Expand); in RISCVTargetLowering()
139 setOperationAction(ISD::UREM, MVT::i32, Custom); in RISCVTargetLowering()
840 case ISD::UREM: in getRISCVWOpcode()
912 case ISD::UREM: in ReplaceNodeResults()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 792 case ISD::UREM: in canOpTrap()
1604 case URem: return ISD::UREM; in InstructionOpcodeToISD()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 89 setOperationAction(ISD::UREM, VT, Expand); in BPFTargetLowering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 135 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
141 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 146 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
147 setOperationAction(ISD::UREM, MVT::i16, Expand); in AVRTargetLowering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 524 setTargetDAGCombine(ISD::UREM); in NVPTXTargetLowering()
4543 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
4770 case ISD::UREM: in PerformDAGCombine()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4656 case ISD::UREM: in selectRem()
5175 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
5176 return selectRem(I, ISD::UREM); in fastSelectInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 177 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) { in WebAssemblyTargetLowering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 311 setOperationAction(ISD::UREM, VT, Expand); in AMDGPUTargetLowering()
381 setOperationAction(ISD::UREM, VT, Expand); in AMDGPUTargetLowering()
1808 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1428 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
|