Home
last modified time | relevance | path

Searched refs:VAddr0Idx (Results 1 – 5 of 5) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNNSAReassign.cpp170 int VAddr0Idx = in CheckNSA() local
176 const MachineOperand &Op = MI.getOperand(VAddr0Idx + I); in CheckNSA()
272 int VAddr0Idx = in runOnMachineFunction() local
279 const MachineOperand &Op = MI->getOperand(VAddr0Idx + I); in runOnMachineFunction()
DSIShrinkInstructions.cpp230 int VAddr0Idx = in shrinkMIMG() local
253 const MachineOperand &Op = MI.getOperand(VAddr0Idx + i); in shrinkMIMG()
296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
297 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef); in shrinkMIMG()
298 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()
301 MI.RemoveOperand(VAddr0Idx + 1); in shrinkMIMG()
DSIInstrInfo.cpp3654 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode, in verifyInstruction() local
3668 bool IsNSA = SRsrcIdx - VAddr0Idx > 1; in verifyInstruction()
3676 VAddrWords = SRsrcIdx - VAddr0Idx; in verifyInstruction()
3678 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx); in verifyInstruction()
6028 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getInstSizeInBytes() local
6029 if (VAddr0Idx < 0) in getInstSizeInBytes()
6033 return 8 + 4 * ((RSrcIdx - VAddr0Idx + 2) / 4); in getInstSizeInBytes()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp374 int VAddr0Idx = in getInstruction() local
378 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; in getInstruction()
379 if (VAddr0Idx >= 0 && NSAArgs > 0) { in getInstruction()
385 MI.insert(MI.begin() + VAddr0Idx + 1 + i, in getInstruction()
470 int VAddr0Idx = in convertMIMGInst() local
560 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); in convertMIMGInst()
564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; in convertMIMGInst()
583 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); in convertMIMGInst()
586 MI.erase(MI.begin() + VAddr0Idx + AddrSize, in convertMIMGInst()
587 MI.begin() + VAddr0Idx + Info->VAddrDwords); in convertMIMGInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2984 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize() local
2988 assert(VAddr0Idx != -1); in validateMIMGAddrSize()
2991 assert(SrsrcIdx > VAddr0Idx); in validateMIMGAddrSize()
2995 bool IsNSA = SrsrcIdx - VAddr0Idx > 1; in validateMIMGAddrSize()
2997 IsNSA ? SrsrcIdx - VAddr0Idx in validateMIMGAddrSize()
2998 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()