Searched refs:VGPR0 (Results 1 – 9 of 9) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUCallingConv.td | 32 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 64 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 116 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 134 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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D | SIInsertSkips.cpp | 170 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead() 171 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead() 172 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead() 173 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
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D | GCNNSAReassign.cpp | 151 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs() 153 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs()
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D | GCNRegBankReassign.cpp | 287 Reg -= AMDGPU::VGPR0; in getPhysRegBank() 315 Reg -= AMDGPU::VGPR0; in getRegBankMask() 595 unsigned MaxReg = MaxNumRegs + (Bank < NUM_VGPR_BANKS ? AMDGPU::VGPR0 in scavengeReg()
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D | SIInsertWaitcnts.cpp | 124 unsigned VGPR0; member 483 assert(Reg >= RegisterEncoding.VGPR0 && Reg <= RegisterEncoding.VGPRL); in getRegInterval() 484 Result.first = Reg - RegisterEncoding.VGPR0; in getRegInterval() 1487 RegisterEncoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction() 1489 RegisterEncoding.VGPR0 + HardwareLimits.NumVGPRsMax - 1; in runOnMachineFunction()
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D | AMDGPUCallLowering.cpp | 678 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
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D | SOPInstructions.td | 727 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
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D | SIRegisterInfo.cpp | 73 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); in SIRegisterInfo()
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D | SIISelLowering.cpp | 1631 Register Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs() 2075 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
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