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Searched refs:VOP3 (Results 1 – 25 of 32) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td31 field bit VOP3 = 0;
80 // This bit indicates that this is a VOP3 opcode which supports op_sel
143 let TSFlags{10} = VOP3;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
DVOPInstructions.td61 // Using complex patterns gives VOP3 patterns a very high complexity rating,
67 let VOP3 = 1;
69 let AsmVariantName = AMDGPUAsmVariants.VOP3;
108 // Using complex patterns gives VOP3 patterns a very high complexity rating,
114 let VOP3 = 1;
123 let AsmVariantName = AMDGPUAsmVariants.VOP3;
163 // XXX - Is there any reason to distingusih this from regular VOP3
DSIDefines.h37 VOP3 = 1 << 10, enumerator
229 VOP3 = 1, enumerator
DAMDGPU.td478 "Can use one literal in VOP3"
915 string VOP3 = "VOP3";
934 let Name = AMDGPUAsmVariants.VOP3;
DSIInstrInfo.td1441 3))); // VOP3
1511 // Returns the register class to use for sources of VOP3 instructions for the
1599 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1641 // VOP3 with modifiers
1655 // VOP3 with modifiers except src2
1668 // VOP3 without modifiers
1893 // Returns the assembly string for the inputs and outputs of a VOP3
2054 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2383 let ColFields = ["Size", "VOP3"];
2392 let ColFields = ["Size", "VOP3"];
DSIInstrInfo.h422 return MI.getDesc().TSFlags & SIInstrFlags::VOP3; in isVOP3()
426 return get(Opcode).TSFlags & SIInstrFlags::VOP3; in isVOP3()
DVOP3Instructions.td10 // VOP3 Classes
221 // VOP3 INTERP
284 // VOP3 Instructions
DVOP2Instructions.td1143 // VOP3 only.
1154 // VOP3 carry-in, carry-out.
1526 // are VOP2 on SI and VOP3 on VI.
1534 let AsmVariantName = AMDGPUAsmVariants.VOP3;
DSOPInstructions.td525 // TODO: b64 versions require VOP3 change since v_lshlrev_b64 is VOP3
550 // TODO: S_MUL_I32 require V_MUL_LO_I32 from VOP3 change
DVOPCInstructions.td882 // Encoding used for VOPC instructions encoded as VOP3 differs from
999 // Encoding used for VOPC instructions encoded as VOP3 differs from
1229 // Encoding used for VOPC instructions encoded as VOP3
DVOP3PInstructions.td19 // VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
DVOP1Instructions.td154 // TODO: Make profile for this, there is VOP3 encoding also
/third_party/mesa3d/src/amd/compiler/tests/
Dtest_assembler.cpp236 …nstruction> add3{create_instruction<VOP3_instruction>(aco_opcode::v_add3_u32, Format::VOP3, 3, 1)};
254 …nstruction> add3{create_instruction<VOP3_instruction>(aco_opcode::v_add3_u32, Format::VOP3, 3, 1)};
/third_party/mesa3d/src/amd/compiler/
Daco_ir.cpp216 if (instr->format == Format::VOP3) in can_use_SDWA()
276 (Format)(((uint16_t)tmp->format & ~(uint16_t)Format::VOP3) | (uint16_t)Format::SDWA); in convert_to_SDWA()
341 if (instr->format == Format::VOP3) in can_use_DPP()
362 Format format = (Format)(((uint32_t)tmp->format & ~(uint32_t)Format::VOP3) | in convert_to_DPP()
Daco_opcodes.py75 VOP3 = 1 << 11 variable in Format
992 VOP3 = { variable
1125 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod, cls) in default_class(VOP3, InstrClass.V…
1126 opcode(name, gfx7, gfx9, gfx10, Format.VOP3, cls, in_mod, out_mod)
Daco_ir.h101 VOP3 = 1 << 11, enumerator
285 return (Format)((uint32_t)Format::VOP3 | (uint32_t)format); in asVOP3()
1291 constexpr bool isVOP3() const noexcept { return (uint16_t)format & (uint16_t)Format::VOP3; } in isVOP3()
Daco_validate.cpp135 base_format = Format::VOP3; in validate_ir()
144 if (instr->isVOP3() && instr->format != Format::VOP3) { in validate_ir()
DREADME-ISA.md97 ## VOP1 instructions encoded as VOP3
Daco_optimizer.cpp2552 VOP3_instruction* new_instr = create_instruction<VOP3_instruction>(opcode, Format::VOP3, 3, 1); in create_vop3_for_op3()
2869 create_instruction<VOP3_instruction>(aco_opcode::v_bcnt_u32_b32, Format::VOP3, 2, 1)}; in combine_add_bcnt()
3410 create_instruction<VOP3_instruction>(mad_op, Format::VOP3, 3, 1)}; in combine_add_lshl()
4099 create_instruction<VOP3_instruction>(mad_op, Format::VOP3, 3, 1)}; in combine_instruction()
Daco_register_allocation.cpp544 if (instr->format == Format::VOP3) { in add_subdword_operand()
688 if (instr->format == Format::VOP3) { in add_subdword_definition()
/third_party/mesa3d/docs/relnotes/
D21.3.6.rst139 - aco: fix neg(abs(mul(a, b))) if the mul is not VOP3
D20.0.0.rst743 - aco: split read/writelane opcode into VOP2/VOP3 version for SI/CI
2818 - aco: handle VOP3 modifiers when combining a constant comparison's NaN
2841 - aco: allow an extra SGPR with multiple uses to be applied to VOP3
2842 - aco: take advantage of GFX10's constant bus limit and VOP3 literals
2847 - aco: don't move literal to reg when making an instruction VOP3 on
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2662 if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) || in checkTargetMatchPredicate()
2663 (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) || in checkTargetMatchPredicate()
2668 if ((TSFlags & SIInstrFlags::VOP3) && in checkTargetMatchPredicate()
2695 static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3}; in getMatchedVariants()
2711 AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3, in getMatchedVariants()
2821 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0) in validateLdsDirect()
3398 if (!(Desc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P))) in validateVOP3Literal()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp355 !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) { in getInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.cpp306 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3) in printVOPDst()

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