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Searched refs:VOPC (Results 1 – 19 of 19) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_opcodes.py74 VOPC = 1 << 10 variable in Format
873 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, cls, True, False)
879 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.Valu32, True, False)
881 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.Valu32, True, False)
883 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.Valu32, True, False)
885 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.Valu32, True, False)
889 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.Valu32, True, False)
891 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.Valu32, True, False)
893 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.ValuDouble, True, False)
895 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, InstrClass.ValuDouble, True, False)
[all …]
Daco_validate.cpp125 else if ((uint32_t)base_format & (uint32_t)Format::VOPC) in validate_ir()
126 base_format = Format::VOPC; in validate_ir()
146 base_format == Format::VOPC || base_format == Format::VINTRP, in validate_ir()
153 base_format == Format::VOPC, in validate_ir()
162 if (base_format == Format::VOPC) { in validate_ir()
Daco_optimizer.cpp1857 if (instr->format == Format::VOPC && /* don't optimize VOP3 / SDWA / DPP */ in label_instruction()
2170 create_instruction<VOP3_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_ordering_test()
2178 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_ordering_test()
2243 create_instruction<VOP3_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_comparison_ordering()
2252 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_comparison_ordering()
2368 create_instruction<VOP3_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_constant_comparison_ordering()
2377 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_constant_comparison_ordering()
2419 create_instruction<VOP3_instruction>(new_opcode, asVOP3(Format::VOPC), 2, 1); in combine_inverse_comparison()
2429 new_opcode, (Format)((uint16_t)Format::SDWA | (uint16_t)Format::VOPC), 2, 1); in combine_inverse_comparison()
2440 new_opcode, (Format)((uint16_t)Format::DPP16 | (uint16_t)Format::VOPC), 2, 1); in combine_inverse_comparison()
[all …]
Daco_ir.h100 VOPC = 1 << 10, enumerator
291 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
1280 constexpr bool isVOPC() const noexcept { return (uint16_t)format & (uint16_t)Format::VOPC; } in isVOPC()
DREADME-ISA.md260 Any permlane instruction that follows any VOPC instruction.
Daco_assembler.cpp292 case Format::VOPC: { in emit_instruction()
Daco_register_allocation.cpp3011 ((instr->format == Format::VOPC && !(instr->definitions[0].physReg() == vcc)) || in register_allocation()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td30 field bit VOPC = 0;
142 let TSFlags{9} = VOPC;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
DVOPCInstructions.td31 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
48 // VOPC classes
51 // VOPC instructions are a special case because for the 32-bit
96 let VOPC = 1;
129 // This class is used only with VOPC instructions. Use $sdst for out operand
882 // Encoding used for VOPC instructions encoded as VOP3 differs from
883 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
999 // Encoding used for VOPC instructions encoded as VOP3 differs from
1000 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1229 // Encoding used for VOPC instructions encoded as VOP3
[all …]
DSIInstrInfo.td1458 SDWAVopcDst, // VOPC
1865 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1883 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1897 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1962 ""); // use $sdst for VOPC
1982 ""); // use $sdst for VOPC
1996 " vcc", // use vcc token as dst for VOPC instructioins
2013 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2025 "$sdst", // VOPC
2041 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
DSIDefines.h34 VOPC = 1 << 9, enumerator
DSISchedule.td55 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DSIInstrInfo.h438 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
442 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
DAMDGPU.td332 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
344 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
DVOPInstructions.td424 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2819 (SIInstrFlags::VOPC | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0) in validateLdsDirect()
6867 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()
6900 } else if (BasicInstType == SIInstrFlags::VOPC && in cvtSDWA()
6943 case SIInstrFlags::VOPC: in cvtSDWA()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.cpp507 if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) && in printOperand()
/third_party/mesa3d/docs/relnotes/
D20.2.0.rst1266 - aco: remove superflous (bool & exec) if the result comes from VOPC
D21.1.0.rst1387 - aco: value number VOPC instructions with different exec masks