Searched refs:VRC (Results 1 – 6 of 6) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | MachineSSAUpdater.cpp | 61 VRC = MRI->getRegClass(VR); in Initialize() 154 VRC, MRI, TII); in GetValueInMiddleOfBlock() 190 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock() 296 Updater->VRC, Updater->MRI, in GetUndefVal() 307 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | MachineSSAUpdater.h | 45 const TargetRegisterClass *VRC; variable
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 3849 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local 3850 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) in legalizeOpWithMove() 3851 VRC = &AMDGPU::VReg_64RegClass; in legalizeOpWithMove() 3853 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove() 3855 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove() 4222 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local 4223 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR() 4225 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR() 4227 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR() 4228 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR() [all …]
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D | SIRegisterInfo.h | 173 const TargetRegisterClass *VRC) const;
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D | SIRegisterInfo.cpp | 1370 const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass() 1371 switch (getRegSizeInBits(*VRC)) { in getEquivalentSGPRClass()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local 452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg() 456 if (RC && RC != VRC) in ConstrainForSubReg()
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