| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | SwiftErrorValueTracking.cpp | 181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; in propagateVRegs() local
186 VRegs.push_back(std::make_pair( in propagateVRegs()
204 VRegs.size() >= 1 && in propagateVRegs()
206 VRegs.begin(), VRegs.end(), in propagateVRegs()
208 -> bool { return V.second != VRegs[0].second; }) != in propagateVRegs()
209 VRegs.end(); in propagateVRegs()
214 assert(!VRegs.empty() && in propagateVRegs()
217 setCurrentVReg(MBB, SwiftErrorVal, VRegs[0].second); in propagateVRegs()
229 assert(!VRegs.empty() && in propagateVRegs()
234 .addReg(VRegs[0].second); in propagateVRegs()
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| D | MIRVRegNamerUtils.cpp | 30 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) { in getVRegRenameMap() argument
42 for (const auto &VReg : VRegs) { in getVRegRenameMap()
130 std::vector<NamedVReg> VRegs; in renameInstsInMBB() local
143 VRegs.push_back( in renameInstsInMBB()
147 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false; in renameInstsInMBB()
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| D | MIRVRegNamerUtils.h | 62 getVRegRenameMap(const std::vector<NamedVReg> &VRegs);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs, in assignVRegs() argument
43 for (unsigned i = 0; i < VRegs.size(); ++i) in assignVRegs()
44 if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT)) in assignVRegs()
50 SmallVectorImpl<Register> &VRegs) { in setLeastSignificantFirst() argument
52 std::reverse(VRegs.begin(), VRegs.end()); in setLeastSignificantFirst()
57 SmallVector<Register, 4> VRegs; in handle() local
72 VRegs.clear(); in handle()
76 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); in handle()
78 if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0], in handle()
104 bool handleSplit(SmallVectorImpl<Register> &VRegs,
[all …]
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| D | MipsCallLowering.h | 37 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
40 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);
57 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
66 ArrayRef<Register> VRegs) const override;
69 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.h | 42 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
48 ArrayRef<Register> VRegs) const override;
51 ArrayRef<ArrayRef<Register>> VRegs) const;
54 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| D | AMDGPUCallLowering.cpp | 262 const Value *Val, ArrayRef<Register> VRegs, in lowerReturnVal() argument
275 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturnVal()
282 unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT); in lowerReturnVal()
293 ArrayRef<Register> VRegs) const { in lowerReturn()
300 assert(!Val == VRegs.empty() && "Return value without a vreg"); in lowerReturn()
324 if (!lowerReturnVal(B, Val, VRegs, Ret)) in lowerReturn()
438 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArgumentsKernel()
470 ArrayRef<Register> OrigArgRegs = VRegs[i]; in lowerFormalArgumentsKernel()
567 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
574 return lowerFormalArgumentsKernel(B, F, VRegs); in lowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.h | 36 ArrayRef<Register> VRegs) const override;
39 ArrayRef<ArrayRef<Register>> VRegs) const override;
46 ArrayRef<Register> VRegs,
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| D | ARMCallLowering.cpp | 238 const Value *Val, ArrayRef<Register> VRegs, in lowerReturnVal() argument
252 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturnVal()
267 ArrayRef<Register> VRegs) const { in lowerReturn()
268 assert(!Val == VRegs.empty() && "Return value without a vreg"); in lowerReturn()
274 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret)) in lowerReturn()
418 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
452 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 189 ArrayRef<Register> VRegs) const { in lowerReturn()
190 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
194 if (!VRegs.empty()) { in lowerReturn()
204 assert(VRegs.size() == SplitEVTs.size() && in lowerReturn()
209 ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; in lowerReturn()
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
329 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
351 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) in lowerFormalArguments()
354 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
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| D | X86CallLowering.h | 32 ArrayRef<Register> VRegs) const override;
35 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 265 ArrayRef<Register> VRegs, in lowerReturn() argument
269 return lowerReturn(MIRBuilder, Val, VRegs); in lowerReturn()
277 ArrayRef<Register> VRegs) const { in lowerReturn() argument
293 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments() argument
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| D | LegalizerHelper.h | 145 SmallVectorImpl<Register> &VRegs);
150 SmallVectorImpl<Register> &VRegs,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVCallLowering.h | 31 ArrayRef<Register> VRegs) const override;
34 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| D | RISCVCallLowering.cpp | 26 ArrayRef<Register> VRegs) const { in lowerReturn()
39 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.h | 37 ArrayRef<Register> VRegs,
41 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| D | AArch64CallLowering.cpp | 258 ArrayRef<Register> VRegs, in lowerReturn() argument
261 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
265 if (!VRegs.empty()) { in lowerReturn()
277 assert(VRegs.size() == SplitEVTs.size() && in lowerReturn()
289 Register CurVReg = VRegs[i]; in lowerReturn()
418 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
430 ArgInfo OrigArg{VRegs[i], Arg.getType()}; in lowerFormalArguments()
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| D | AArch64InstrAtomics.td | 402 // The fast register allocator used during -O0 inserts spills to cover any VRegs
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 183 auto *VRegs = VMap.getVRegs(Val); in getOrCreateVRegs() local
195 VRegs->push_back(MRI->createGenericVirtualRegister(Ty)); in getOrCreateVRegs()
196 return *VRegs; in getOrCreateVRegs()
205 llvm::copy(EltRegs, std::back_inserter(*VRegs)); in getOrCreateVRegs()
209 VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0])); in getOrCreateVRegs()
210 bool Success = translate(cast<Constant>(Val), VRegs->front()); in getOrCreateVRegs()
217 return *VRegs; in getOrCreateVRegs()
221 return *VRegs; in getOrCreateVRegs()
369 ArrayRef<Register> VRegs; in translateRet() local
371 VRegs = getOrCreateVRegs(*Ret); in translateRet()
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| D | LegalizerHelper.cpp | 124 SmallVectorImpl<Register> &VRegs) { in extractParts() argument
126 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); in extractParts()
127 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
132 SmallVectorImpl<Register> &VRegs, in extractParts() argument
144 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); in extractParts()
145 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
161 VRegs.push_back(NewReg); in extractParts()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCTargetDesc.h | 164 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.h | 163 SmallVectorImpl<unsigned> &VRegs) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 115 return decodeRegisterClass(Inst, RegNo, VRegs); in DecodeVRRCRegisterClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1881 SmallVector<CalleeSavedInfo, 18> VRegs; in processFunctionBeforeFrameFinalized() local
1923 VRegs.push_back(CSI[i]); in processFunctionBeforeFrameFinalized()
2076 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized()
2077 int FI = VRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 464 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
1196 RegNo = VRegs[IntVal]; in MatchRegisterName()
|