Searched refs:VSHL (Results 1 – 14 of 14) sorted by relevance
392 X86_INTRINSIC_DATA(avx2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),393 X86_INTRINSIC_DATA(avx2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),394 X86_INTRINSIC_DATA(avx2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),850 X86_INTRINSIC_DATA(avx512_psll_d_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),851 X86_INTRINSIC_DATA(avx512_psll_q_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),852 X86_INTRINSIC_DATA(avx512_psll_w_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),1056 X86_INTRINSIC_DATA(sse2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),1057 X86_INTRINSIC_DATA(sse2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),1058 X86_INTRINSIC_DATA(sse2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),
309 VSHL, VSRL, VSRA, enumerator
226 def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
23268 case X86ISD::VSHL: in getTargetVShiftUniformOpcode()23270 return IsVariable ? X86ISD::VSHL : X86ISD::VSHLI; in getTargetVShiftUniformOpcode()29719 case X86ISD::VSHL: return "X86ISD::VSHL"; in getTargetNodeName()35382 case X86ISD::VSHL: in SimplifyDemandedVectorEltsForTargetNode()35394 return (UseOpc == X86ISD::VSHL || UseOpc == X86ISD::VSRL || in SimplifyDemandedVectorEltsForTargetNode()35685 case X86ISD::VSHL: in SimplifyDemandedVectorEltsForTargetNode()39607 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() || in combineVectorShiftVar()46029 case X86ISD::VSHL: in PerformDAGCombine()
501 // represented by intrinsics in LLVM, and even the basic VSHL variable shift502 // operation cannot be safely translated to LLVM's shift operators. VSHL can509 // shifts, where the constant is replicated. For consistency with VSHL (and
113 VSHL, enumerator
1289 case AArch64ISD::VSHL: return "AArch64ISD::VSHL"; in getTargetNodeName()7707 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) in tryLowerToSLI()8343 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0), in LowerVectorSRA_SRL_SHL()10800 Opcode = AArch64ISD::VSHL; in tryCombineShiftImm()
461 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
4600 enum NeonShiftOp { VSHL, VSHR, VSLI, VSRI, VSRA }; enumerator4605 DCHECK_EQ(op, VSHL); in EncodeNeonShiftRegisterOp()4626 case VSHL: { in EncodeNeonShiftOp()4678 emit(EncodeNeonShiftOp(VSHL, NeonDataTypeToSize(dt), false, NEON_Q, in vshl()4687 emit(EncodeNeonShiftRegisterOp(VSHL, dt, NEON_Q, dst.code(), src.code(), in vshl()
1135 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;1139 "VSHL(s|u)(v16i8|v8i16|v4i32|v2i64)")>;
561 "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF",
5834 // VSHL : Vector Shift5879 // VSHL : Vector Shift Left (Immediate)
10241 // FastEmit functions for AArch64ISD::VSHL.10276 …case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op…10395 // FastEmit functions for AArch64ISD::VSHL.10430 …case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op…10683 // FastEmit functions for AArch64ISD::VSHL.10718 …case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0…10807 // FastEmit functions for AArch64ISD::VSHL.10842 …case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op…
14626 // FastEmit functions for X86ISD::VSHL.15219 case X86ISD::VSHL: return fastEmit_X86ISD_VSHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);