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Searched refs:VirtReg (Results 1 – 25 of 28) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign()
107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
122 Register PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign()
125 VRM->clearVirt(VirtReg.reg); in unassign()
[all …]
DRegAllocFast.cpp86 Register VirtReg; ///< Virtual register number. member
91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
94 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
193 void killVirtReg(Register VirtReg);
195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg);
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
204 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
207 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
208 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
213 MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
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DRegAllocBasic.cpp103 unsigned selectOrSplit(LiveInterval &VirtReg,
117 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
144 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) { in INITIALIZE_PASS_DEPENDENCY()
145 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
146 if (VRM->hasPhys(VirtReg)) { in INITIALIZE_PASS_DEPENDENCY()
159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
160 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
164 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
204 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
212 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
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DRegAllocGreedy.cpp255 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
256 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
261 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
465 unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
469 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
473 LiveInterval &VirtReg, SlotIndex Start,
477 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
489 unsigned isSplitBenefitWorthCost(LiveInterval &VirtReg);
491 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
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DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
90 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
95 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
96 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs()
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
108 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); in allocatePhysRegs()
113 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
120 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
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DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference()
105 return is_contained(InterferingVRegs, VirtReg); in isSeenInterference()
DVirtRegMap.cpp101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { in hasPreferredPhys() argument
102 Register Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
107 return getPhys(VirtReg) == Hint; in hasPreferredPhys()
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { in hasKnownPreference() argument
111 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
314 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
315 if (MRI->reg_nodbg_empty(VirtReg)) in addMBBLiveIns()
317 LiveInterval &LI = LIS->getInterval(VirtReg); in addMBBLiveIns()
322 Register PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns()
517 Register VirtReg = MO.getReg(); in rewrite() local
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DAllocationOrder.cpp29 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder() argument
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) in AllocationOrder()
DRegisterCoalescer.h62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair() argument
64 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} in CoalescerPair()
DLiveDebugVariables.cpp427 UserValue *lookupVirtReg(unsigned VirtReg);
477 void mapVirtReg(unsigned VirtReg, UserValue *EC);
603 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg() argument
604 assert(Register::isVirtualRegister(VirtReg) && "Only map VirtRegs"); in mapVirtReg()
605 UserValue *&Leader = virtRegToEqClass[VirtReg]; in mapVirtReg()
609 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg() argument
610 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) in lookupVirtReg()
1193 Register VirtReg = Loc.getReg(); in rewriteLocations() local
1194 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations()
1195 Register::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations()
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DInlineSpiller.cpp543 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { in reMaterializeFor() argument
546 VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg, &Ops); in reMaterializeFor()
552 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
558 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
574 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor()
582 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor()
598 if (!canGuaranteeAssignmentAfterRemat(VirtReg.reg, MI)) { in reMaterializeFor()
599 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor()
623 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
DAllocationOrder.h43 AllocationOrder(unsigned VirtReg,
DRegAllocBase.h104 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
DMachineBasicBlock.cpp509 Register VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
510 if (!MRI.constrainRegClass(VirtReg, RC)) in addLiveIn()
512 return VirtReg; in addLiveIn()
516 Register VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
517 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) in addLiveIn()
521 return VirtReg; in addLiveIn()
DTargetRegisterInfo.cpp383 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints() argument
391 MRI.getRegAllocationHints(VirtReg); in getRegAllocationHints()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveRegMatrix.h107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
119 void assign(LiveInterval &VirtReg, unsigned PhysReg);
124 void unassign(LiveInterval &VirtReg);
139 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
144 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
DVirtRegMap.h127 bool hasPreferredPhys(Register VirtReg);
132 bool hasKnownPreference(Register VirtReg);
148 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
149 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
150 return Orig ? Orig : VirtReg; in getOriginal()
DLiveIntervalUnion.h91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
157 bool isSeenInterference(LiveInterval *VirtReg) const;
DScheduleDAGInstrs.h53 unsigned VirtReg; member
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
61 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
DRegisterPressure.h535 bool hasUntiedDef(unsigned VirtReg) const { in hasUntiedDef() argument
536 return UntiedDefs.count(VirtReg); in hasUntiedDef()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp77 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints() argument
88 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
93 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg)) in getRegAllocationHints()
98 if (VirtReg == Use.getOperand(0).getReg()) { in getRegAllocationHints()
103 } else if (VirtReg == Use.getOperand(1).getReg()) { in getRegAllocationHints()
106 } else if (VirtReg == Use.getOperand(2).getReg() && in getRegAllocationHints()
122 MRI->getRegClass(VirtReg)); in getRegAllocationHints()
136 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) { in getRegAllocationHints()
139 Worklist.push_back(VirtReg); in getRegAllocationHints()
178 for (MachineInstr &DefMI : MRI->def_instructions(VirtReg)) in getRegAllocationHints()
DSystemZRegisterInfo.h61 bool getRegAllocationHints(unsigned VirtReg,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp128 const Register VirtReg = MO.getReg(); in rewriteRegs() local
129 if (Register::isPhysicalRegister(VirtReg)) in rewriteRegs()
132 if (!VRM->hasPhys(VirtReg)) in rewriteRegs()
135 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp301 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints() argument
308 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); in getRegAllocationHints()
319 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); in getRegAllocationHints()
DARMBaseRegisterInfo.h152 bool getRegAllocationHints(unsigned VirtReg,

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